Multiple Clock Cycles Research Articles

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version

We study a new transistor-level side-channel leakage caused by charges trapped in between stacked transistors namely residual electric charges (RECs). Building leakage models is important in designing countermeasures against side-channel attacks (SCAs). The conventional work showed that even a transistor-level leakage is measurable with a local electromagnetic measurement. One example is the current-path leak [1], [2]: an attacker can distinguish the number of transistors in the current path activated during a signal transition. Addressing this issue, Sugawara et al. proposed to use a mirror circuit that has the same number of transistors on its possible current paths. We show that this countermeasure is insufficient by showing a new transistor-level leakage, caused by RECs, not covered in the previous work. RECs can carry the history of the gate's state over multiple clock cycles and changes the gate's electrical behavior. We experimentally verify that RECs cause exploitable side-channel leakage. We also propose a countermeasure against REC leaks and designed advanced encryption standard-128 (AES-128) circuits using IO-masked dual-rail read-only memory with a 180-nm complementary metal-oxide-semiconductor (CMOS) process. We compared the resilience of our AES-128 circuits against EMA attacks with and without our countermeasure and investigated an RECs' effect on physically unclonable functions (PUFs). We further extend RECs to physically unclonable function. We demonstrate that RECs affect the performance of arbiter and ring-oscillator PUFs through experiments using our custom chips fabricated with 180- and 40-nm CMOS processes*.

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing

There is an emerging need to design multi-precision floating-point (FP) accelerators for high-performance-computing (HPC) applications. The commonly-used methods are based on high-precision-split (HPS) and low-precision-combination (LPC) structures, which suffer from low hardware utilization ratio and various multiple clock-cycle processing periods. In this brief, a new multi-precision FP processing element (PE) is developed with proposed bit-partitioning method. Minimized redundant bits and operands are achieved. The proposed PE supports <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> half-precision (FP16), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> single-precision (FP32) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times $ </tex-math></inline-formula> double-precision (FP64) operations with 100% multiplication hardware utilization ratio. Besides, vector systolic structure is designed for PE array to increase the system-level throughput and energy efficiency. The proposed design is realized in a 28-nm process with 1.351-GHz clock frequency. Compared with the existing multi-precision FP methods, the proposed work exhibits the best energy-efficiency performance of 1193 GFLOPS/W at FP16, 317 GFLOPS/W at FP32 and 77.3 GFLOPS/W at FP64 with at least 22.3%, 30% and 3.3% improvement, respectively.

Securing InfiniBand Networks with the Bluefield-2 Data Processing Unit

Interest in securing InfiniBand networks with encryption is growing. However, the performance benefit realized by InfiniBand’s use of Direct Memory Access (DMA) to bypass the kernel and avoid intervention from host Central Processing Units (CPUs) is at odds with IP datagram encryption techniques. Encryption forces data through the CPU before transmission and decryption, incurring multiple clock cycles. The Bluefield-2 Data Processing Unit (DPU) is Nvidia-Mellanox’s latest system on chip that combines a high-performance, programmable processor, network interface card (NIC), and flexible hardware accelerators. This research characterizes the Bluefield-2’s capability to accelerate IPsec encryption in hardware. Results show that the Bluefield-2’s hardware accelerators are capable of supporting a secure IPsec tunnel with a throughput of nearly 16 Gb/s. Offloading IPsec encryption operations to the hardware accelerators on the Bluefield-2 is a promising method for adding confidentiality, integrity, and authentication to InfiniBand networks.

A Long Duration Transient Resilient Pipeline Scheme

Single event transients (SETs) in combinational logic remain an important topic in the reliability domain. SETs were traditionally relatively short in comparison to the clock period. The majority of the countermeasures utilizes this property. However, advances in technology scaling will reverse the ratio for complementary metal-oxide semiconductor devices. Investigations show that SETs may last up to multiple clock cycles in the future. So-called long duration transients (LDTs) corrupt almost all available countermeasures. This paper presents a new methodology to tackle LDTs. Dual modular redundancy (DMR) is used to detect any corruption of the application logic. A new micro-rollback scheme expands the DMR architecture with fault correction capabilities. The concept is also capable of handling single event upsets and timing violations. The correction penalty is two clock cycles. The approach was implemented and verified in a Viterbi decoder architecture. The scheme utilizes a newly designed History Cell. The History Cell introduces an area overhead of 97% and a power overhead of 110%, compared to a standard cell DFF.

Beat-to-beat control of human optokinetic nystagmus slow phase durations.

This study provides the first clear evidence that the generation of optokinetic nystagmus (OKN) fast phases is a decision process that is influenced by performance of a concurrent disjunctive reaction time task (DRT). The slow phase (SP) durations are consistent with a Gaussian basic interval generator and multiple interval SP durations occur more frequently in the presence of the DRT. Hence, OKN shows dual-task interference in a manner observed in voluntary movements, such as saccades.

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS’89 benchmark circuits show that our method is more accurate and efficient than previous methods.

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Single-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressive out-of-order execution by extensively enlarging the instruction window resources to exploit memory-level parallelism (MLP). However, simply enlarging the window resources lengthens the clock cycle time. Although pipelining the resources solves this problem, it in turn prevents instruction-level parallelism (ILP) from being exploited because issuing instructions requires multiple clock cycles. This paper proposed a dynamic scheme that adaptively resizes the instruction window based on the predicted available parallelism, either ILP or MLP. Specifically, if the scheme predicts that MLP is available during execution, the instruction window is enlarged and the window resources are pipelined, thereby exploitingMLP. Conversely, if the scheme predicts that less MLP is available, that is, ILP is exploitable for improved performance, the instruction window is shrunk and the window resources are de-pipelined, thereby exploiting ILP. Our evaluation results using the SPEC2006 benchmark programs show that the proposed scheme achieves nearly the best performance possible with fixed-size resources. On average, our scheme realizes a performance improvement of 21% over that of a conventional processor, with additional cost of only 6% of the area of the conventional processor core or 3% of that of the entire processor chip. The evaluation results also show 8% better energy efficiency in terms of 1/EDP (energy-delay product). key words: microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism

Analysis of Error Masking and Restoring Properties of Sequential Circuits

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits, such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of state transitions with respect to correlations between the restoring inputs and time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementations when designing FSMs.

A Clock Reaction Based on Molybdenum Blue

Clock reactions are rare kinetic phenomena, so far limited mostly to systems with ionic oxoacids and oxoanions in water. We report a new clock reaction in cyclohexanol that forms molybdenum blue from a noncharged, yellow molybdenum complex as precursor, in the presence of hydrogen peroxide. Interestingly, the concomitant color change is reversible, enabling multiple clock cycles to be executed consecutively. The kinetics of the clock reaction were experimentally characterized, and by adding insights from quantum chemical calculations, a plausible reaction mechanism was postulated. Key elementary reaction steps comprise sigmatropic rearrangements with five-membered or bicyclo[3.1.0] transition states. Importantly, numerical kinetic modeling demonstrated the mechanism's ability to reproduce the experimental findings. It also revealed that clock behavior is intimately connected to the sudden exhaustion of hydrogen peroxide. Due to the stoichiometric coproduction of ketone, the reaction bears potential for application in alcohol oxidation catalysis.

An efficient sparse matrix format for accelerating regular expression matching on field-programmable gate arrays

Regular expression matching is widely used in many programming languages and applications. A regular expression is transformed into a deterministic finite automata DFA for processing. However, the DFA requires large memory resources because of the state blowup problem. Many algorithms have been proposed to compress the DFA storage and generally store the compressed DFA in sparse matrix format. For field-programmable gate array FPGA-based implementations, operations on sparse matrix consume multiple clock cycles, thus reducing the flexibility and performance of applications. To accelerate the regular expression matching, we present a compact sparse matrix format for storing the compressed DFA transition table on the FPGA. Taking advantage of the special properties of sparse matrices generated by DFAs, we can accomplish one access within a single clock cycle. Furthermore, we develop a regular expression matching engine on a Xilinx Xilinx Inc. Location: 2100 Logic Dr, San Jose, CA 95124-3400, USA Virtex-6 FPGA chip using this sparse matrix format. Compared with previous solutions, this regular expression matching engine has more flexibility while keeping high compression ratio. The results show that this regular expression matching engine saves 94% of memory space compared with the original DFA structure while keeping a fast matching speed. By running multiple engines in parallel, our design achieves a throughput up to 29Gbps. Copyright ©2013 John Wiley & Sons, Ltd.

Designing of 8-bit Synchronous FIFO Memory using Register File

FIFO is implies first in first out using queue methodology for memories read and write of any information and data using some control logic. The whole work of FIFO is fully dependent on the control circuitry and clock domain. It is often used to control the flow of data from source to destination by the transition of every clock. Basically FIFO differentiate by clock domain either Synchronous or Asynchronous. There are various methods to designing and synthesized FIFO but here fully focused on the memory which is used to store the data in domain of clock either sync. and async. or single and multiple clock cycles. This paper will differentiate the design, synthesize and analyze a Synchronous FIFO using Register file memory by older version of Synchronous FIFO. In this paper, conclude the effect of using register file instead of random access memory for storage of data in FIFO memory. This work shows change the parameters like on-chip components (clock, signal, input and outputs etc), clock domain, type of resources, and how to minimize and optimize hierarchy of the device. The RTL description for the FIFO is written using Verilog HDL (hardware description language). And design is simulated and synthesizes in Xilinx ISE Design suit 12. 4. The RTL code simulated in ISim Simulator.

On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests

Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.

Timing variation-aware scheduling and resource binding in high-level synthesis

Due to technological scaling, process variations have increased significantly, resulting in large variations in the delay of the functional units. Hence, the worst-case approach is becoming increasingly pessimistic in meeting a certain performance yield. The problem therefore is to increase the performance as much as possible while maintaining the desired yield. In this work, we introduce an integer linear programming (ILP) formulation for scheduling and resource binding in high-level synthesis (HLS) which tries to mitigate the effect of timing variations. In the presence of delay variations of resources, as chained resources can give a better latency and performance yield trade-off, instead of considering them independently, we consider external chaining of resources, that is, two or more resources are connected by external wiring, and exploit operation chaining. Without violating the yield constraints, the proposed ILP formulation chains two consecutive operations and binds these chained operations to chained resources for minimizing the overall latency of the schedule. Our ILP formulation also makes sure that two consecutive operations can be chained over multiple clock cycles so that it becomes possible to access the data in the middle of the chained operations at the start of the clock steps over which the operations are chained. By solving our ILP formulation using ILOG CPLEX, we show that our mechanism achieves lesser latency in most cases, compared to the no-chaining case. Significant performance improvement is achieved even for the 100% yield case, which has never been demonstrated in any published work, to the best of our knowledge.

Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking

In this paper, we present a post-silicon self-correction technique to leverage the redundancy present in parallel prefix adders (PPA). Our technique is based on the fact that a set of carries in PPAs can be made mutually exclusive. Therefore, defects in a set of bits can only corrupt the corresponding set of Sum outputs whereas the remaining Sums are computed correctly. To efficiently utilize the above property of PPAs in presence of defects, we perform addition in multiple clock cycles. In cycle-1, one of the correct set of bits are computed and stored at the output registers. In the subsequent cycles, the operands are shifted by one bit at a time and the remaining sets of bits are recovered. This allows us to compute the correct output at the cost of throughput degradation and minor area and delay overhead while maintaining high frequency and yield. Finally, the proposed technique is used in a superscalar processor, whereby the self-correcting adder is assigned lower priority than fault-free adders to reduce the overall throughput degradation.

A Simple Digital DCM Control Scheme for Boost PFC Operating in Both CCM and DCM

Digital average current controllers for boost power factor correctors (PFCs) are usually designed for continuous conduction mode (CCM). However, discontinuous conduction mode (DCM) appears in the inductor current near the zero crossings of the input current at light loads, resulting in input current distortion. It is caused by inaccurate average current values obtained in DCM and by the linear CCM PFC controller that is unable to ensure input current shaping in DCM whereby the converter exhibits nonlinear characteristic. This paper proposes a simple digital DCM control scheme that is achieved with minimal changes to the CCM average current control structure. It is mathematically and computationally simple. The result of all arithmetic operations in the proposed current control loop to obtain the desired control output can be achieved in a single clock cycle, whereas other DCM control schemes require multiple clock cycles. Good input current shaping is achieved in both CCM and DCM with the proposed CCM-DCM digital controller.

A compact microchip atomic clock based on all-optical interrogation of ultra-cold trapped Rb atoms

We propose a compact atomic clock that uses all-optical interrogation of ultra-cold Rb atoms that are magnetically trapped near the surface of an atom microchip. The interrogation scheme, which combines electromagnetically induced transparency with Ramsey’s method of separated oscillatory fields, can achieve an atomic shot-noise-level performance better than \(10^{-13}/\sqrt{\tau}\) for 106 atoms. A two-color Mach–Zehnder interferometer can detect a 100-pW probe beam at the optical shot-noise level using conventional photodetectors. This measurement scheme is nondestructive and therefore can be used to increase the operational duty cycle by reusing the trapped atoms for multiple clock cycles. Numerical calculations of the density matrix equations are used to identify realistic operating parameters at which AC Stark shifts are eliminated. By considering fluctuations in these parameters, we estimate that AC Stark shifts can be canceled to a level better than 2×10−14. An overview of the apparatus is presented with estimates of cycle time and power consumption.

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

We present a method to design high-throughput fully parallel low-density parity-check (LDPC) decoders. With our method, a decoder's longest wires are divided into several short wires with pipeline registers. Log-likelihood ratio messages transmitted along with these pipelined paths are thus sent over multiple clock cycles, and the decoder's critical path delay can be reduced while maintaining comparable bit error rate performance. The number of registers inserted into paths is estimated by using wiring information extracted from initial placement and routing information with a conventional LDPC decoder, and thus only necessary registers are inserted. Also, by inserting an even number of registers into the longer wires, two different codewords can be simultaneously decoded, which improves the throughput at a small penalty in area. We present our design flow as well as post-layout simulation results for several versions of a length-1024, (3,6)-regular LDPC code. Using our technique, we achieve a maximum uncoded throughput of 13.21 Gb/s with an energy consumption of 0.098 nJ per uncoded bit at E b/N0 = 5 dB. This represents a 28% increase in throughput, a 30% decrease in energy per bit, and a 1.6% increase in core area with respect to a conventional parallel LDPC decoder, using a 90-nm CMOS technology.

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

As Globally Asynchronous and Locally Synchronous (GALS) based System-on-chip (SoC) are gaining importance, a special case of GALS when the global clocking is preserved, but the interconnect delays of multiple clock cycles are to be tolerated has also been proposed, and used. In some cases, such designs, known as Latency-Insensitive Protocol (LIP) based SoC integration are also general enough to work when the global clocking is not present. In either case, the protocols are complex, and many optimized implementations of such protocols need verification that indeed they work correctly with respect to the specification of the system. Usually the specification of the system is fully globally clocked with negligible interconnect delays, so that the specification can be first implemented as synchronous design with traditional tools. GALS or LIP refinements are then applied to tolerate the multi-cycle interconnect delays, or fully asynchronous interconnect communication, as the case may be. Verifying that such refinements are correctness preserving, researchers have used model checking in the past. In this paper, we present static analysis based framework for such verification. Our framework makes use of the Polychrony framework and associated semantic analysis techniques, in the form of endo-isochrony. We show a number of LIP protocols to preserve the correctness with respect to their fully synchronous specifications using our framework. We believe, designers can verify LIP implementations with clever optimizations using our framework much more readily than when using model checking.

Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits

In this paper, we describe a new transition fault model for synchronous sequential circuits. Similar to previous models, it addresses the fact that delayed signal-transitions span multiple clock cycles when a test sequence is applied at-speed. It addresses this issue in a different way than earlier models. The model requires the activation of single stuck-at faults with opposite stuck-at values on the same line <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> at consecutive time units. In addition, it requires the detection of both faults (as single faults) at the same or later time units. Due to the activation of the faults at consecutive time units, there is a 1 rarr 0 or 0 rarr 1 transition at the fault site <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> . Since both faults are eventually detected, a deviation from the expected value at either the first or second time unit due to a delay fault on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> or due to transitions that started earlier and did not settle will be (or is likely to be) detected. The model can be used together with other models to increase the confidence that delay defects will be detected. As an added advantage, the model helps detect other types of faults that require two-pattern tests, such as transistor stuck-open faults.

Survey of Scan Chain Diagnosis

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.