Multilevel Resistive Random Access Memory Research Articles

Heterogeneous integrated InP/SiC high-performance multilevel RRAM

With the advent of the Age of Big Data, resistive random-access memory (RRAM) shows considerable potential for next generation nonvolatile storage technologies owing to its simplified structure, high switching speed, and low power consumption. However, mainstream prepared materials, such as oxides and halide perovskite, face critical issues for practical applications such as switching uniformity and long-term environmental stability. In this work, we report that high carrier mobility material indium phosphide (InP) is prepared as an RRAM medium and is directly bonded to the high thermal conductivity substrate silicon carbide (SiC) at 200 °C, overcoming large (14.9%) lattice mismatch. Importantly, the bonding strength reaches 9.3 MPa, and this high-performance stable RRAM exhibits nonvolatile and reliable switching characteristics including stable endurance (200 cycles) and long data retention (2000 s). Moreover, multilevel storage is also available by modulating RESET stop voltages. This work provides broad possibilities for high-performance RRAM with structures based on traditional semiconductors in the field of nonvolatile storage.

Highly Reliable 3D Channel Memory and Its Application in a Neuromorphic Sensory System for Hand Gesture Recognition.

Brain-inspired neuromorphic computing systems, based on a crossbar array of two-terminal multilevel resistive random-access memory (RRAM), have attracted attention as promising technologies for processing large amounts of unstructured data. However, the low reliability and inferior conductance tunability of RRAM, caused by uncontrollable metal filament formation in the uneven switching medium, result in lower accuracy compared to the software neural network (SW-NN). In this work, we present a highly reliable CoOx-based multilevel RRAM with an optimized crystal size and density in the switching medium, providing a three-dimensional (3D) grain boundary (GB) network. This design enhances the reliability of the RRAM by improving the cycle-to-cycle endurance and device-to-device stability of the I-V characteristics with minimal variation. Furthermore, the designed 3D GB-channel RRAM (3D GB-RRAM) exhibits excellent conductance tunability, demonstrating high symmetricity (624), low nonlinearity (βLTP/βLTD ∼ 0.20/0.39), and a large dynamic range (Gmax/Gmin ∼ 31.1). The cyclic stability of long-term potentiation and depression also exceeds 100 cycles (105 voltage pulses), and the relative standard deviation of Gmax/Gmin is only 2.9%. Leveraging these superior reliability and performance attributes, we propose a neuromorphic sensory system for finger motion tracking and hand gesture recognition as a potential elemental technology for the metaverse. This system consists of a stretchable double-layered photoacoustic strain sensor and a crossbar array neural network. We perform training and recognition tasks on ultrasonic patterns associated with finger motion and hand gestures, attaining a recognition accuracy of 97.9% and 97.4%, comparable to that of SW-NN (99.8% and 98.7%).

Optimizing multi-level ReRAM memory for low latency and low energy consumption

Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.

Hybrid Precision in Resistive Memory-Based Convolutional Kernel for Fault-Resilient Neuromorphic Systems

As simple convolution computation is intensively and iteratively performed to extract features from input images, cross-point arrays with resistive random access memory (RRAM) serving as a kernel weight can accelerate the relevant mathematical operations in hardware. However, considering actual RRAM characteristics, either variability or unexpected permanent failure from the filamentary switching mechanism is observed, degrading recognition performance. This study investigates the impact of fault in a conventional kernel structure, where two adjacent columns in the array represent a single weight, on feature extraction using MATLAB. First, the fault types of HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\textit{x}}$</tex-math> </inline-formula> -based multilevel RRAM is categorized. The results reveal that the unidirectional fault of RRAM primarily worsens the accuracy of image recognition. This is because the subtraction of negative weights from positive ones is crucial for identifying the edges of images through convolution operations. Therefore, we exploit a kernel structure, in which a single column dedicated to negative weights is located next to a matrix of positive weights. In addition, we reduce the weight precision for negative weights, while quantizing positive weights to higher bits. By mitigating the subtraction errors achieved by the kernel structure with hybrid precision, we improved fault tolerance, minimizing accuracy degradation.

MR-PIPA: An Integrated Multilevel RRAM (HfO x )-Based Processing-In-Pixel Accelerator

This work paves the way to realize a processing-in-pixel (PIP) accelerator based on a multilevel HfOx resistive random access memory (RRAM) as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarse-grained convolution operation in low-bit-width neural networks (NNs) leveraging a novel compute-pixel with nonvolatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs. Our proposed design, namely an integrated multilevel RRAM (HfOx)-based processing-in-pixel accelerator (MR-PIPA), achieves a frame rate of 1000 and efficiency of ~1.89 TOp/s/W, while it substantially reduces data conversion and transmission energy by ~84% compared to a baseline at the cost of minor accuracy degradation.

Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy

Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy

Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy

Crossbars of resistive memories, or memristors, provide a road to reduce the energy consumption of artificial neural networks, by naturally implementing multiply accumulate operations, their most basic calculations. However, a major challenge of implementing robust hardware neural networks is the conductance instability over time of resistive memories, due to the local recombination of oxygen vacancies. This effect causes resistive memory‐based neural networks to rapidly lose accuracy, an issue that is sometimes overlooked. Herein, this conductance instability issue is shown, which can be avoided without changing the material stack of the resistive memory by exploiting an original programming strategy. This technique relies on program‐and‐verify loops with appropriately chosen wait times and ensures that the resistive memories are programmed into states with stable filaments. To test the strategy, a 32 × 32 in‐memory computing system, fabricated in a hybrid complementary metal‐oxide‐semiconductor (CMOS)/hafnium oxide technology, is programmed to classify heart arrhythmia from electrocardiogram. When the resistive memories are programmed conventionally, the system loses accuracy within hours. In contrast, when using this technique, the system maintains an accuracy of 95% over more than 2 months. These results highlight the potential of resistive memory for the implementation of low‐power neural networks with long‐term stability.

Polymerized hybrid Hf-based hydroquinone/Al2O3 bilayer structure by molecular/atomic layer deposition for non-volatile resistive random access memory

In this work, we fabricated the Pt/Hf-based hydroquinone (Hf-HQ)/Al2O3/TiN/Si bilayer hybrid memory by molecular layer deposition/atomic layer deposition. The hybrid memory units exhibit electroforming-free bipolar resistive switching (RS) characteristics with tiny fluctuation of operation voltages within 0.2 V, ON/OFF ratio above 102, and good endurance/retention properties. Meanwhile, the multi-state data storage capability is confirmed in hybrid devices. The RS mechanism based on conducting filaments has been proposed. The favorable linkage and rupture of the conducting filament prefer to occur at the interface of the hybrid Hf-HQ layer and Al2O3 layer, resulting in the brilliant performances. Furthermore, flexible hybrid memory devices fabricated on bendable mica show comparable RS behaviors to the Si-based ones at the bending radius of 7.5 mm, indicative of great potential in flexible multilevel resistive random access memory applications.

Reliable Resistive Switching and Synaptic Behaviors Based on a TiOx‐Doped N Memristor for Information Storage and Neuromorphic Computing

Bipolar resistive switching (RS) and synaptic behaviors of resistive random access memory (RRAM) based on TiO x are demonstrated. RS uniformity is improved by introducing nitrogen into the RS layer using radio frequency sputtering in the reactive Ar/N2 ambient. The conductive mechanism is in good agreement with the space−charge‐limited conduction model. The activation energy fit by the Arrhenius equation and conductive atomic force microscopy results indicate that the conductive filaments are formed by oxygen vacancies. More importantly, reliable multilevel RRAM can be achieved by tuning the compliance current, which enables the achievement of distinguishable resistance states. Furthermore, multilevel RRAM enables the simulation of synaptic functions, such as learning−forgetting−relearning, habituation, and spike‐timing‐dependent plasticity (STDP). Image pattern recognition based on STDP learning rules using a digital memristor is demonstrated. The findings may offer a route to the development of future storage and neuromorphic computing.

Improvement of State Stability in Multi-Level Resistive Random-Access Memory (RRAM) Array for Neuromorphic Computing

In this work, a new operation scheme is developed to improve the state stability of multi-level resistive random-access memory (RRAM) array. We found that the state instability after programming is mainly derived from the excessive oxygen vacancies generated by the abrupt SET process. Based on the understanding of the state stability after operation, triangular pulse is adopted for the programming of multi-level RRAM, which can effectively suppress the short-term relaxation and improve the long-time retention. Comparison results show that the degradation on recognition accuracy of Cifar-10 over time in ResNet18 network reduces from 8.07% by using square pulse programming to 0.93% by utilizing the proposed operation scheme.

RRAM for Compute-in-Memory: From Inference to Training

To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.

Multilevel resistive random access memory achieved by MoO3/Hf/MoO3 stack and its application in tunable high-pass filter

In this work, the multilevel resistive random access memories (RRAMs) have been achieved by using the structure of Pt/MoO3/Hf/MoO3/Pt with four stable resistance states. The devices show good retention property of each state (>104 s) and large memory window (>104). The simulation and experimental study reveal that the resistive switching mechanism is ascribed to combination of the conductive filament in the stack of MoO3/Hf next to the top electrode and redox reaction at the interface of Hf/MoO3 next to bottom electrode. The fitting results of current–voltage characteristics under low sweep voltage indicate that the conduction of HRSs is dominated by the Poole–Frenkel emission and that of LRS is governed by the Ohmic conduction. Based on the RRAM, the tunable high-pass filter (HPF) with configurable filtering characteristics has been realized. The gain-frequency characteristics of the programmable HPF show that the filter has high resolution and wide programming range, demonstrating the viability of the multilevel RRAMs for future spiking neural network and shrinking the programmable filters with low power consumption.

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine

Accurate cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM)-based compute-in-memory inference engines. To tighten the distribution of the cells of each state, we developed a two-step write–verify scheme within a limited number of iterations, which was tested on a test vehicle based on HfO2 RRAM array to realize 2 bits per cell. The conductance of the cells is gathered in the targeted range within 10 loops of set and reset processes for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intermediate state cells under relatively high read voltage (e.g. 0.2 V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5 bit ADC that is required for a 128 × 128 array with 2 bits per cell.

Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.

Uniform multilevel switching of graphene oxide-based RRAM achieved by embedding with gold nanoparticles for image pattern recognition

Traditional metal-oxide semiconductor devices are inadequate for use in artificial neural networks (ANNs) owing to their high power consumption, complex structures, and difficult fabrication techniques. Resistive random access memory (RRAM) is a promising candidate for ANNs owing to its simple structure, low power consumption, and excellent compatibility with CMOS. Moreover, it can mimic synaptic functions because of its multilevel resistive switching (RS) behavior. Herein, we demonstrate highly uniform RS and a high on/off ratio of RRAM based on graphene oxide by embedding gold nanoparticles into the device. This allowed reliable multilevel storage. Further, multilevel RRAM based on spike-timing-dependent-plasticity learning rules was used for image pattern recognition. These findings may offer a route to develop reliable digital memristors for ANNs.

Highly reliable multilevel resistive switching in a nanoparticulated In2O3 thin-film memristive device

The present report deals with the development of a cost-effective, solution-processable and nanoparticulated In2O3 thin-film memristive device for application in multilevel resistive random access memory (RRAM). The structural, morphological, elemental and electrical characterizations are carried out with the help of x-ray diffractometry, scanning electron microscopy, photoluminescence spectroscopy, Fourier transform infrared spectroscopy, x-ray photoelectron spectroscopy and a memristor characterization system. The electrical characterizations reveal that the nanoparticulated In2O3 thin-film memristive device is free from the electroforming process and shows self-rectifying and self-compliance memory effects. Furthermore, we have demonstrated multilevel resistive switching with excellent memory properties of endurance (10 000 switching cycles) and retention (2 ks). Interestingly, the device shows a good memory window (10 for all cases), and multilevel resistance states are not degraded during endurance and retention memory tests. The uniformity and stability in multilevel resistive switching are further confirmed by statistical calculations. Furthermore, the nanoparticulated In2O3 thin-film memristive device mimics the property of paired-pulse facilitation of a biological synapse. A detailed analysis of electrical results suggests that the Schottky effect is responsible for the device conduction. In a nutshell, the nanoparticulated In2O3 memristive device is suitable for future multilevel RRAM application and is a promising candidate for development of an electronic synaptic device for application in neuromorphic computing.

Convolutional Neural Networks Based on RRAM Devices for Image Recognition and Online Learning Tasks

In this paper, we devise and optimize schemes for the resistive random-access memory (RRAM)-based hardware implementation of convolutional neural networks (CNNs). The key achievements are as follows: 1) a specific circuit for CNN and corresponding operation methods is presented; 2) quantization schemes for utilizing binary RRAM or RRAM with multilevel resistances as synapses are proposed, and simulations show that our CNN system percentage accuracy for the MNIST data set using multilevel RRAM and 97% accuracy using binary RRAM as synapses; 3) the influence of factors such as the number and size of kernels, as well as the device conductance variation, on the final recognition accuracy is discussed. Three ways to reduce the hardware cost are also analyzed; and 4) we implement the online learning function using the developed CNN system with a binary spike-time-dependent plasticity protocol and achieve up to 94% accuracy for the online learning tasks.

Intensity-modulated LED achieved through integrating p-GaN/n-ZnO heterojunction with multilevel RRAM

We developed an intensity-modulated light-emitting device (LED) by integrating a p-GaN/n-ZnO heterojunction with multilevel resistive random access memory (RRAM). In this device, the luminous intensity of LED can be adjusted through regulating the injection current according to the variable resistance state of RRAM. As one critical foundation of device fabrication, uniform operation of multilevel RRAM was achieved by inserting carbon quantum dots into HfO2−x RRAM as a local-electric-field regulator. Eventually, the reversible regulation of electroluminescence intensity was demonstrated by tuning the compliance current in the modulated LED. Thanks to the simple structure and nanoscale switching region, this modulated LED may offer a feasible method to replace traditional thin film transistors or CMOSs with complicated structures and techniques, enabling the potential application of low-cost and high-density LED displays.

Highly uniform switching of HfO2−x based RRAM achieved through Ar plasma treatment for low power and multilevel storage

We demonstrated an effective method of Ar surface plasma treatment (SPT) to improve the resistive switching (RS) uniformity of HfO2−x based resistive random access memory (RRAM) device. More importantly, the operation of multilevel RRAM and low power consumption can be further achieved by reliable RS, which enabled to obtain five distinguishable low resistance states and can be operated with a low power consumption of ∼30 pJ. The results of atomic force microscope and X-ray photoelectron spectroscopy analysis confirmed that the Ar SPT induced more oxygen defects and higher roughness on the surface, which decreased the migration barrier of oxygen migration and some tips below the electrode. Eventually, a moderate forming process and local electric-field enhancement around these tips were obtained, accounting for the improvement of RS uniformity. This method could be promising to develop RRAM with high uniformity for the low-power multilevel memory applications.