Multidimensional Parity Research Articles

An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

Multidimensional Parity Algorithms to Escalate the Security of Intelligent Mobile Models in Education

The traditional multiple reserves and resounding costs of increase of the corporal volume can be replaced by a distributed file model of divided data employing algorithms, multidimensional integrity, and resilience to complete losses of the storage facilities. The model's created duplicated data enables you to recover some of the split components' lost functionality. A rapid shift in the appraisal and application of knowledge is also required by increasing information and communication technologies. As a result, modern learning methodologies, approaches, and technologies are being developed. This paper describes how to build an automated instructional and analytical complex using semantic information. It has been established what is needed for such an educational and technological complex. Tools built on a semantic network are represented in formal and structural models. Since it was created using a thorough understanding of the topic, the model is intended to facilitate students' perception of the many educational and technical complexities and to enhance the teacher's work.

Improving the Security of Split Data When Using Multidimensional Parity Algorithms

A model of distributed storage split data using algorithms, multidimensional parity, resistance to partial losses of the storage sites, is regarded as an alternative way of security that can replace the conventional multiple reservations and carrying costs of growth of the physical volume. In this model, the generated redundant data allows you to restore partial loss of the split parts. In this case, the recovery is performed at the expense of the parity files formed during the splitting procedure, in which the main action is the calculation of bitwise parity with summation modulo "two". With this additional operation between the source files, you can restore the corrupted file without distortion. A comparison with several models that use checksum codes for recovery shows that the estimated probability of losses due to storage failure in the case of multidimensional parity codes is significantly less than when using other split data storage options. Using the operation of adding the bits of undamaged files, you can completely restore corrupted files. According to the calculated data, even when theoretically non-recoverable losses are reached, it is always possible to find combinations of chain recovery. The complexity of alternative methods, including the iterative decoding method, makes a distributed split data storage system using multidimensional parity algorithms a more convenient error correction technology.
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An integrated fault detection and exclusion scheme to support aviation navigation

This paper proposes a novel integrity monitoring scheme against global navigation satellite systems (GNSS) fault for civil aviation navigation. The main contributions are (a) developing an efficient user algorithm that integrates fault detection and exclusion (FDE) functions, and (b) deriving the analytical methods to quantify its corresponding integrity risk. The intended application of the new scheme is advanced receiver autonomous integrity monitoring (ARAIM), which is proposed by the United States (U.S.) and European Union (E.U.), and will serve as the next generation of the main aviation navigation means. In this new approach, the exclusion decision-making process is unified into the first layer detection step, thereby dramatically improving efficiency. The principle of this method is utilizing the multi-dimensional parity vector projections in parity space to extract the information of faults. In this work, we derive the projection matrix for single satellite failure modes, establish the mechanism for determining exclusion subset based on the projection magnitudes, and rigorously account for the false exclusion probabilities in the integrity risk quantification. The feasibility of the algorithm is verified and validated using Monte-Carlo simulations, and the performance is analyzed by evaluating the integrity risk. It is shown that the new FDE scheme can efficiently and effectively exclude the faulty satellites as desired, while achieving promising navigation performance.

Testing of Information Storage System Using Multidimensional Parity Algorithms Resistant to Partial Loss of Storage Locations

Testing of Information Storage System Using Multidimensional Parity Algorithms Resistant to Partial Loss of Storage Locations

Utilization of multi-dimensional source correlation in multi-dimensional single parity check codes

This paper proposes a joint source-channel coding (JSCC) technique that well utilizes multi-dimensional (MD) source correlation using MD single parity check codes (MD-SPCCs). The source is assumed to be described by the coupling of multiple first-order binary Markov processes. The knowledge about the source correlation is utilized in the channel decoding process where each component decoder utilizes a single dimension correlation of the MD source. To enhance performance and reduce the error floor, a rate-1 recursive systematic convolutional code is serially concatenated to the MD-SPCC via a random interleaver. Two decoding techniques are proposed for each component decoder, and the selection of the decoding technique depends on the strength of the source correlation, which may further enhance the performance of the proposed JSCC technique. Simulation results reveal that a significant performance gain can be achieved by exploiting the MD source correlation with the proposed JSCC technique compared with the case in which the source correlation is not utilized; more significant gains can be achieved with stronger source correlation, and with a larger dimensionality source correlation as well.

High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity

It is well-known that a significant fraction of server power is consumed in memory; this is especially the case for servers with chipkill correct memories. We propose a new chipkill correct memory organization that decouples correction of errors due to local faults that affect a single symbol in a word from correction of errors due to device-level faults that affect an entire column, sub-bank, or device. By using a combination of two codes that separately target these two fault modes, the proposed chipkill correct organization reduces code overhead by half as compared to conventional chipkill correct memories for the same rank size. Alternatively, this allows the rank size to be reduced by half while maintaining roughly the same total code overhead. Simulations using PARSEC and SPEC benchmarks show that, compared to a conventional double chipkill correct baseline, the proposed memory organization, by providing double chipkill correct at half the rank size, reduces power by up to 41%, 32% on average over a conventional baseline with the same chipkill correct strength and access granularity that relies on linear block codes alone, at only 1% additional code overhead.

Error and flow control in terabit intelligent optical backplanes

The design of a free-space optical backplane which supports error and flow control functions is described. Traditionally, these functions are implemented in custom high-speed electronic application specific integrated circuits, which are physically removed from the optical interconnect layer. In this paper, we consider migrating these functions directly into the optoelectronic layer, yielding an "intelligent optical backplane." Conventional error control protocols are infeasible with optical backplanes since they require excessive amounts of hardware. The design of an efficient error control protocol based upon a multidimensional parity check, along with the effective flow control protocol is proposed and analyzed. The key blocks of the protocol have been implemented in 0.8- and 0.5-/spl mu/m CMOS/SEED devices and are summarized. The protocols require significantly less hardware than alternative schemes, and smart pixel arrays supporting these protocols are scalable to higher bandwidths and lower latencies. A very large scale integration analysis indicates that using 2004 technology, a free-space backplane can potentially be clocked at 1 GHz and support 24 Tb/s of bandwidth. Finally, the proposed error control protocols should be useful in optical disks and holographic memory systems, which also perform error control on large two-dimensional arrays of optical bits.