Multi-core Heterogeneous System Research Articles

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Program Inputs

A hardware configuration is a set of processors and their frequency levels in a multicore heterogeneous system. This article presents a compiler-based technique to match functions with hardware configurations. Such a technique consists of using multivariate linear regression to associate function arguments with particular hardware configurations. By showing that this classification space tends to be convex in practice, this article demonstrates that linear regression is not only an efficient tool to map computations to heterogeneous hardware, but also an effective one. To demonstrate the viability of multivariate linear regression as a way to perform adaptive compilation for heterogeneous architectures, we have implemented our ideas onto the Soot Java bytecode analyzer. Code that we produce can predict the best configuration for a large class of Java and Scala benchmarks running on an Odroid XU4 big.LITTLE board; hence, outperforming prior techniques such as ARM’s GTS and CHOAMP, a recently released static program scheduler.

RACECAR

High-performance computing systems increasingly combine multi-core processors and heterogeneous resources such as graphics-processing units and field-programmable gate arrays. However, significant application design complexity for such systems has often led to untapped performance potential. Application designers targeting such systems currently must determine how to parallelize computation, create device-specialized implementations for each heterogeneous resource, and determine how to partition work for each resource. In this paper, we present the RACECAR heuristic to automate the optimization of applications for multi-core heterogeneous systems by automatically exploring implementation alternatives that include different algorithms, parallelization strategies, and work distributions. Experimental results show RACECAR-specialized implementations achieve speedups up to 117x and average 11x compared to a single CPU thread when parallelizing computation across multiple cores, graphics-processing units, and field-programmable gate arrays.

Parallel ray casting algorithm based on muti-core cell processors

How to make full use of high performance of multi-core heterogeneous platform to support practical application is becoming a new research hotspot. Take graphic algorithms for example, depending on balance allocation study of Ray Casting, the paper proposed a designing method to develop a parallel ray casting application in Cell B. E multi-core heterogeneous system with function decomposition and the row-block static allocation. SMID method was used to optimize the performance. Testing results show that the speedup and scalability is fine, and the performance in Cell is 14 times better than SMP server.

Electronic system, platform, and package codesign

Integrating multicore heterogeneous systems into a system-in-package has challenged many design and test engineers. To overcome these obstacles, we need a common EDA tool for digital, analog, RF, and thermal designs. This article proposes a platform-centric design methodology for modern electronic systems that could incorporate system-on-chip, system-in-package, and system-on-package technologies