Multi-bit Signals Research Articles

3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing

We propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. We then demonstrate a method for placing multiple contacts on a relay that can reduce contact resistance variation by 40× over a circular placement strategy. Additionally, we develop static and dynamic SPICE models (calibrated to accurate finite element models) for predicting circuit-level performance with these devices. Finally, we establish a methodology for integrating these relays into an industry-standard digital design flow. Using our multi-pole relay design, we perform post-layout simulation of a hybrid CMOS-NEMS CGRA processing element (PE) tile in 40 nm technology. We achieve up to 19% lower area and 10% lower power at iso-delay, compared to a CMOS-only CGRA PE tile. The results show a way to bridge the performance gap between programmable logic devices (such as CGRAs) and application-specific integrated circuits using NEMS technology.

Simultaneous Wireless Power and Multibit Signals Transfer System With Hybrid Modulation Waves PWM Control

Simultaneous Wireless Power and Multibit Signals Transfer System With Hybrid Modulation Waves PWM Control

Integration of very long baseline interferometry data acquisition, recording, and transmission with multichannel and multibit for CE-5 mission

<p indent="0mm">Real-time signal acquisition, recording, and transmission are the important functions of very long baseline interferometry (VLBI). In the Chang’e-5 (CE-5) mission, a VLBI backend is required to connect the telemetry, track and command (TT&amp;C) beacons, data signals from multiple probes, such as the orbiter, ascender, and lander, and signals from the extragalactic radio source in time. Due to the multiple frequency points, large dynamic range, and complex spectrum form of the probe signals, existing VLBI astronomical backends do not meet the requirements of lunar exploration and deep space exploration. According to the characteristics of the beacon of CE-5 probes, we researched the integration technology of multichannel and multibit signal acquisition, recording, and transmission. This paper proposes a frequency tunable polyphase-filter bank algorithm, which can flexibly set frequency and obtain flat amplitude and linear phase characteristics in a wide band. The novel integrated VLBI backend developed by this technology contains 16 channels, which can sample and record all the TT&amp;C and data signals from CE-5 probes in real time and transmit the VLBI data to the VLBI center through the network. It ensures successful VLBI measurement in the complex electromagnetic environment of CE-5 multi beacons. Compared with the previous astronomical backends, the real-time performance, measurement accuracy, and reliability of the novel integrated VLBI backend are greatly improved, which support the successful completion of China’s first lunar sampling return mission of CE-5. The novel integrated VLBI backend also has the function of multibit quantization to meet the needs of wide and narrow observation of future radio sources and probes.

Characteristic Analysis of Monobit Signal

This paper analyzes the characters of monobit signals and gives the reason why the spurious free dynamic ranges (SFDR) of monobit signals is much lower than those of multi-bit signals. According to our analysis and simulation, if the third harmonic of a monobit signal can be filtered, the SFDR of it can be improved well. Therefore, we give the way to obtain the desired band, which do not contain any third harmonics, and the simulation results are in agreement with our design. Such way can be used to improve the performance of monobit digital receivers in engineering.

Multifunctional Random-Laser Smart Inks.

With the superiority of laser-level intensity, narrow spectral line width, and broad-angular emission, random lasers (RLs) have drawn considerable research interests for their potential to carry out a variety of applications. In this work, the applications associated with optical-encoded technologies, including security printing, military friend or foe identification (FFI), and anticounterfeiting of documents are highlighted, and the concept of a transient RL "smart ink" has been proposed. The proof-of-concept was demonstrated as invisible signatures, which encoded the messages through the spectral difference of spontaneous emission and RL under specified conditions. Next, the possibility of encoding the data with multibit signals was further confirmed by exploiting the threshold tunability of RLs. Moreover, the transient characteristic of this smart ink and its capability to be attached on freeform surfaces of different materials were also shown. With the advantages of a facile manufacturing process and multiple purposes, it is expected that this ink can soon be carried out in a variety of practical utilities.

MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem

We present MNCaRT, a comprehensive software ecosystem for the study and use of automata processing across hardware platforms. Tool support includes manipulation of automata, execution of complex machines, high-speed processing of NFAs and DFAs, and compilation of regular expressions. We provide engines to execute automata on CPUs (with VASim and Intel Hyperscan), GPUs (with custom DFA and NFA engines), and FPGAs (with an HDL translator). We also introduce MNRL, an open-source, general-purpose and extensible state machine representation language developed to support MNCaRT. The representation is flexible enough to support traditional finite automata (NFAs, DFAs) while also supporting more complex machines, such as those which propagate multi-bit signals between processing elements. We hope that our ecosystem and representation language stimulates new efforts to develop efficient and specialized automata processing applications.

Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented applications that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be effectively exploited to reduce the implementation area of datapath circuits on FPGAs that employ the traditional bidirectional routing. Most of modern FPGAs, however, employ unidirectional routing tracks which are more area and delay efficient. No study has investigated the design of multi-bit routing architectures to effectively transport multiple-bit wide signals using unidirectional routing tracks. This paper presents such an investigation of architectures which employ multi-bit connections and unidirectional routing resources to exploit datapath regularity. It is experimentally shown that unidirectional multi-bit routing architectures are 8.6% more area efficient than the conventional routing architecture. This paper also determines the most area efficient proportion of multi-bit routing tracks.

The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications. Large arithmetic intensive applications often contain a large proportion of datapath circuits. Since datapath circuits are designed to process multiple-bit-wide data, FPGAs implementing these circuits often have to transport a large amount of multiple-bit-wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. In this work, we investigate the area efficiency of FPGA routing resources for transporting multiple-bit-wide signals. It is shown that, for datapath circuits, the switch patterns used by the conventional routing architecture, which uniformly distribute routing switches across the routing tracks, are inefficient for connecting the computing elements to their tracks. The more efficient multi-bit aware patterns, which contain a densely populated single-bit region and a sparsely populated multi-bit region, can be effectively used to reduce the routing area of FPGAs for implementing arithmetic intensive applications by 6%-10%. It is also shown that the further sharing of configuration memory among the switches within the multi-bit aware patterns does not significantly increase their area efficiency since datapath circuits typically contain a mixture of multi-bit and single-bit signals-while configuration memory sharing can substantially increase the area efficiency of routing resources for transporting multi-bit signals, it also significantly reduces their ability for transporting single-bit signals. More importantly, configuration memory sharing can significantly reduce the effectiveness of the enhanced multi-bit aware patterns-patterns that incorporate both multi-bit aware and single-bit oriented switches within a single region in order to increase its ability for transporting both single-bit and multi-bit signals.

Analog-to-digital conversion using noise shaping and time encoding

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators. </para>

Distortion-Free 1-Bit PWM Coding for Digital Audio Signals

Although uniformly sampled pulse width modulation (UPWM) represents a very efficient digital audio coding scheme for digital-to-analog conversion and full-digital amplification, it suffers from strong harmonic distortions, as opposed to benign nonharmonic artifacts present in analog PWM (naturally sampled PWM, NPWM). Complete elimination of these distortions usually requires excessive oversampling of the source PCM audio signal, which results to impractical realizations of digital PWM systems. In this paper, a description of digital PWM distortion generation mechanism is given and a novel principle for their minimization is proposed, based on a process having some similarity to the dithering principle employed in multibit signal quantization. This conditioning signal is termed jither and it can be applied either in the PCM amplitude or the PWM time domain. It is shown that the proposed method achieves significant decrement of the harmonic distortions, rendering digital PWM performance equivalent to that of source PCM audio, for mild oversampling (e.g., ×4) resulting to typical PWM clock rates of 90MHz.

Adaptive Delta-Sigma Modulation for Enhanced Input Dynamic Range

An adaptive delta-sigma modulator of 1st order with one-bit quantization is presented. Adaptation is instantaneous and based on an exponential law. The feedback signal is a multibit discrete-level signal generated by a digital-to-analog converter (DAC). Compared to a nonadaptive delta-sigma modulator of 1st order, the input dynamic range is significantly enhanced. The gain in dynamic range is 6 dB per bit defining the feedback amplitude. The influence of nonideal DAC performance is discussed. It is demonstrated that an implementation of the system is realistic with standard CMOS technology. To relax the requirements to the one-bit quantizer, the quantizer input signal is amplified adaptively (Q-Switching).

Adaptive algorithm for ternary filtering

Despite their major advantage of hardware simplicity, ternary filters have limited usability in practice owing to their unresolved problem of adaptivity. This challenging problem is tackled by introducing an adaptive ternary LMS-like algorithm. Performance assessment using a sinusoidal input distorted by additive white Gaussian noise showed that the proposed algorithm is comparable to the traditional multi-bit Wiener LMS algorithm. This approach is expected to open the door for ternary systems to be ready for replacing multi-bit signal processing systems.

Near-Field Sound-Source Localization Based on a Signed Binary Code

This paper proposes near-field sound-source localization based on crosscorrelation of a signed binary code. The signed binary code eliminates multibit signal processing for simpler implementation. Explicit formulae with near-field assumption are derived for a two microphone scenario and extended to a three microphone case with front-rear discrimination. Adaptive threshold for enabling and disabling source localization is developed for robustness in noisy environment. The proposed sound-source localization algorithm is implemented on a fixed-point DSP. Evaluation results in a robot scenario demonstrate that near-field assumption and front-rear discrimination provides almost 40% improvement in DOA estimation. A correct detection rate of 85% is obtained by a robot in a home environment.

Efficient digital single-bit resonator

An all-digital single-bit resonator is presented. The resonator input can be either a single-bit or multi-bit signal and the resonator output is in single-bit format. This resonator structure contains no multi-bit multiplication operations, making the resonator efficient for implementation.

Digital processing of Doppler sonar signals

The signal processing gain by digital beamforming in Doppler sonar was investigated in terms of the enhancement of signal-to-reverberation ratio (SRR) at the postbeamforming Doppler-filter output with an objective to determine the minimum number of bits necessary for the quantization of beamformer channel input signals without appreciable degradation of sonar performance. The formulation of the problem follows closely the author’s earlier work which extends Davenport’s analysis of bandpass limiter to the more general multichannel multibit signal processors. Owing to the Doppler shift of target signal frequency and the relatively narrow bandwidth of Doppler filters, we express the frequency selective effect in the nonlinear interacting power series in terms of a new set of coefficients cmk, which bear crucial significance in sonar performance. Extensive numerical calculations of ’’Doppler processing gain’’ were carried out to demonstrate that four-bit quantization of array transducer signals is theoretically sufficient to yield a performance essentially identical to that of a linear beamformer, but severe loss of gain could result if fewer than four bits are taken at the quantizer output. It is further demonstrated numerically and substantiated analytically that, for small input SRR, the processing gain of a digital beamformer with Doppler filters cannot exceed that of a linear (or optimized four-bit digital) beamformer even it its channel signals are quantized into more than four bits.

Signal-processing gain by digital beamforming in Doppler sonar

The signal-processing gain by digital beamforming in Doppler sonar was investigated in terms of the enhancement of signal-to-reverberation ratio (SRR) at the post-beamforming Doppler filter output with an objective to determine the minimum number of bits necessary for the quantization of beamformer channel input signals without appreciable degradation of sonar performance. It is shown that, in the present case, the simplified method of counting spectral lobes originally due to Davenport [W. B. Davenport Jr., J. Appl. Phys. 24, 720 (1953); for application to multichannel multibit signal processors, see H. S. C. Wang, J. Acoust. Soc. Am. 53, 929 (1973)] can only be applied with certain modifications in the evaluation of various signal and reverberation interacting power terms. Extensive numerical calculations of “Doppler processing gain” were then carried out to demonstrate that four-bit quantization of array transducer signals is theoretically sufficient to yield a performance essentially identical to that of a linear beamformer, but severe loss of gain could result if fewer than four bits are taken at the quantizer output. It is further demonstrated numerically and substantiated analytically that, for small input SRR, the processing gain of a digital beamformer with Doppler filters cannot exceed that of a linear (or optimized four-bit digital) beamformer even if its channel signals are quantized into more than four bits.