Multi-writer Multi-reader Registers Research Articles

Polylogarithmic concurrent data structures from monotone circuits

This article presents constructions of useful concurrent data structures, including max registers and counters, with step complexity that is sublinear in the number of processes, n . This result avoids a well-known lower bound by having step complexity that is polylogarithmic in the number of values the object can take or the number of operations applied to it. The key step in these implementations is a method for constructing a max register , a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the largest value previously written. For fixed m , an m -valued max register is constructed from one-bit multi-writer multi-reader registers at a cost of at most ⌈log m ⌉ atomic register operations per write or read. An unbounded max register is constructed with cost O (min(log v , n )) to read or write a value v . Max registers are used to transform any monotone circuit into a wait-free concurrent data structure that provides write operations setting the inputs to the circuit and a read operation that returns the value of the circuit on the largest input values previously supplied. One application is a simple, linearizable, wait-free counter with a cost of O (min(log n log v , n )) to perform an increment and O (min(log v , n )) to perform a read, where v is the current value of the counter. For polynomially-many increments, this becomes O (log 2 n ), an exponential improvement on the best previously known upper bounds of O ( n ) for exact counting and O ( n 4/5+ϵ ) for approximate counting. Finally, it is shown that the upper bounds are almost optimal. It is shown that for deterministic implementations, even if they are only required to satisfy solo-termination, min(⌈log m ⌉, n -1) is a lower bound on the worst-case complexity for an m -valued bounded max register, which is exactly equal to the upper bound for m ≤ 2 n -1 , and min( n -1, ⌈ log m ⌉ - log(⌈ log m ⌉ + k )) is a lower bound for the read operation of an m -valued k -additive-accurate counter, which is a bounded counter in which a read operation is allowed to return a value within an additive error of ± k of the number of increment operations linearized before it. Furthermore, even in a solo-terminating randomized implementation of an n -valued max register with an oblivious adversary and global coins, there exist simple schedules in which, with high probability, the worst-case step complexity of a read operation is Ω(log n /log log n ) if the write operations have polylogarithmic step complexity.

Tight bounds for asynchronous randomized consensus

A distributed consensus algorithm allows n processes to reach a common decision value starting from individual inputs. Wait-free consensus, in which a process always terminates within a finite number of its own steps, is impossible in an asynchronous shared-memory system. However, consensus becomes solvable using randomization when a process only has to terminate with probability 1. Randomized consensus algorithms are typically evaluated by their total step complexity , which is the expected total number of steps taken by all processes. This article proves that the total step complexity of randomized consensus is Θ( n 2 ) in an asynchronous shared memory system using multi-writer multi-reader registers. This result is achieved by improving both the lower and the upper bounds for this problem. In addition to improving upon the best previously known result by a factor of log 2 n , the lower bound features a greatly streamlined proof. Both goals are achieved through restricting attention to a set of layered executions and using an isoperimetric inequality for analyzing their behavior. The matching algorithm decreases the expected total step complexity by a log n factor, by leveraging the multi-writing capability of the shared registers. Its correctness proof is facilitated by viewing each execution of the algorithm as a stochastic process and applying Kolmogorov's inequality.

Adaptive and Efficient Algorithms for Lattice Agreement and Renaming

In a shared-memory system, n independent asynchronous processes, with distinct names in the range {0, ..., N-1}, communicate by reading and writing to shared registers. An algorithm is wait-free if a process completes its execution regardless of the behavior of other processes. This paper considers wait-free algorithms whose complexity adjusts to the level of contention in the system: An algorithm is adaptive (to total contention) if its step complexity depends only on the actual number of active processes, k; this number is unknown in advance and may change in different executions of the algorithm. Adaptive algorithms are presented for two important decision problems, lattice agreement and (6k-1)-renaming; the step complexity of both algorithms is O(k log k). An interesting component of the (6k-1)-renaming algorithm is an O(N) algorithm for (2k-1)-renaming; this improves on the best previously known (2k-1)-renaming algorithm, which has O(Nnk) step complexity. The efficient renaming algorithm can be modified into an O(N) implementation of atomic snapshots using dynamic single-writer multi-reader registers. The best known implementations of atomic snapshots have step complexity O(N log N) using static single-writer multi-reader registers, and O(N) using multi-writer multi-reader registers.

Efficient and Robust Sharing of Memory in Message-Passing Systems

A simulation of a wait-free, atomic, single-writer multireader register in an asynchronous message passing system is presented. The simulation can withstand the failure of up to half of the processors and requires O(n) messages (for each read or write operation), assuming there are n+1 processors in the system. It improves on the previous simulation, which requires O(n2) messages (for each read or write operation). The message complexity of the new simulation is within a constant factor of the optimum. The new simulation improves the complexity of algorithms for the following problems in the message-passing model in the presence of processor failures: multiwriter multireader registers, concurrent time-stamp systems, ℓ-exclusion, atomic snapshots, randomized consensus, implementation of data structures, as well as improved fault-tolerant algorithms for any solvable decision task.

Sharing memory robustly in message-passing systems

Emulators that translate algorithms from the shared-memory model to two different message-passing models are presented. Both are achieved by implementing a wait-free, atomic, single-writer multi-reader register in unreliable, asynchronous networks. The two message-passing models considered are a complete network with processor failures and an arbitrary network with dynamic link failures.These results make it possible to view the shared-memory model as a higher-level language for designing algorithms in asynchronous distributed systems. Any wait-free algorithm based on atomic, single-writer multi-reader registers can be automatically emulated in message-passing systems, provided that at least a majority of the processors are not faulty and remain connected. The overhead introduced by these emulations is polynomial in the number of processors in the system.Immediate new results are obtained by applying the emulators to known shared-memory algorithms. These include, among others, protocols to solve the following problems in the message-passing model in the presence of processor or link failures: multi-writer multi-reader registers, concurrent time-stamp systems,l-exclusion, atomic snapshots, randomized consensus, and implementation of data structures.