Multithreaded Processor Research Articles

ISeq: an integrated tool to fetch public sequencing data.

High-throughput sequencing technologies [next-generation sequencing (NGS)] are increasingly used to address diverse biological questions. Despite the rich information in NGS data, particularly with the growing datasets from repositories like the Genome Sequence Archive (GSA) at NGDC, programmatic access to public sequencing data and metadata remains limited. We developed iSeq to enable quick and straightforward retrieval of metadata and NGS data from multiple databases via the command-line interface. iSeq supports simultaneous retrieval from GSA, SRA, ENA, and DDBJ databases. It handles over 25 different accession formats, supports Aspera downloads, parallel downloads, multi-threaded processes, FASTQ file merging, and integrity verification, simplifying data acquisition and enhancing the capacity for reanalyzing NGS data. iSeq is freely available on Bioconda (https://anaconda.org/bioconda/iseq) and GitHub (https://github.com/BioOmics/iSeq).

SMT efficiency in supervised ML methods: a throughput and interference analysis

The microarchitecture of general-purpose processors is continuously evolving to adapt to the new computation and memory demands of incoming workloads. In this regard, new circuitry is added to execute specific instructions like vector multiplication or string operations. These enhancements and the support of multiple threads per core make simultaneous multithreading (SMT) processors dominate the market for data center processors. Regarding emerging workloads, machine learning is taking an important role in many research domains like biomedicine, economics, and social sciences. This paper analyzes the efficiency of machine learning workloads running in SMT mode (two threads per core) versus running them in ST mode (single-threaded) with twice the number of cores. Experimental results in an Intel Xeon Skylake-X processor show an SMT efficiency falling between 80% and 100% across the studied workloads. These results prove two main findings: i) last-generation SMT processors are excellent candidates to execute ML workloads as they achieve a high SMT efficiency, and ii) if the performance of two major resources (i.e., FP double operator and core’s caches) was boosted, all the workloads would achieve an almost perfect SMT efficiency. Moreover, results show that there is still room to support more threads without adding extra hardware. The discussed findings are aimed at providing insights to design future processors for ML workloads.

Ultra-stretchable triboelectric touch pad with sandpaper micro-surfaces for Transformer-assisted gesture recognition

Touch pad based on triboelectric nanogenerator are attracting attention in the field of wearable electronics and human-machine interaction. However, it is still a challenge to realize touch pads combining large-area metamorphic stretchability, high power triboelectric sensing, intelligent free-sliding recognition and availability in extreme environments. Here, we fabricate an ultra-stretchable triboelectric touch pad by integrating liquid metal and high performance hydrogel-based triboelectric sensor arrays, which achieves Transformer-assisted gesture recognition for drone flight direction control. The internal hydrogel electrode has great stretchability, electrical conductivity and anti-freeze properties. Encapsulated in Ecoflex with sandpaper micro-surfaces, it endows high triboelectric power density and pressure sensitivity. With screen-printed liquid metal, the integrated touch pad is fully ultra-stretchable and large-area strain stability. Combining Internet of Things, we build a Transformer-assisted human machine interface. Notably, slide gesture signal peak deviation is reduced by integral processing. The random free-sliding gesture signals are parsed by the Transformer algorithm with 96.83 % accuracy. Multi-threaded signal processing improves the response speed and throughput of the system. The accurate real-time gesture recognition for drone flight direction control in extreme environment is realized. This human machine interface can facilitate development of next generation intelligent remote interactive platforms.

Handheld structured light system for panoramic 3D measurement in mesoscale

Abstract The measurement of complete 3D topography in mesoscale plays a vital role in high-precision reverse engineering, oral medical modeling, circuit detection, etc. Traditional structured light systems are limited to measuring 3D shapes from a single perspective. How to achieve high-quality mesoscopic panoramic 3D measurement remains challenging, especially in complex measured scenarios such as dynamic measurement, scattering medium, and high reflectance. To overcome these problems, we develop a handheld mesoscopic panoramic 3D measurement system for such complex scenes together with the fast point-cloud-registration and accurate 3D-reconstruction, where a motion discrimination mechanism is designed to ensure that the captured fringe is in a quasi-stationary case by avoiding the motion errors caused during fringe scanning; a deep neural network is utilized to suppressing the fringe-degradation caused by scattering mediums resulting to significantly improves the quality of the 3D point cloud; a strategy based on phase averaging is additionally proposed to simultaneously correct the saturation-induced errors and gamma nonlinear errors. Finally, the proposed system with a multi-threaded data processing framework is further developed to verify the proposed method and the corresponding experiments verify its feasibility.

Design of Container Module for Stable Multi-thread Processing of Radar SW

Design of Container Module for Stable Multi-thread Processing of Radar SW

Memory Dependence Speculation for Simultaneous Multi-Threading Processors

Simultaneous Multi-Threading (SMT) processors provide improvement over the traditional out-of-order superscalar architecture by allowing instructions from several independent threads to execute out-of-order concurrently. Maintaining the accuracy of values read from and written to memory is a great bottleneck for processor performance, as loads must stall execution until all prior store addresses are known or risk reading invalid data. Prior research in this area has mainly focused on superscalar architecture, as such, it is only natural to extend memory dependence speculation techniques to an SMT architecture. In this paper, we allow for loads among threads to execute as soon as their addresses are resolved without checking for prior memory address conflicts. Stores also perform a check on all later loads to see if any read was too early due to an address match, if so, the processor state is recovered, and the load re-issued. This aggressive technique allows for the greatest potential instructions per clock cycle gains over predictive techniques as the pipeline is never stalled for loads. Our simulations show that an overall IPC gain up to 12% and 10% is possible for both 4-threaded and 8-threaded workloads respectively. Conversely, a maximum overall IPC loss of at least 2.3% and 2% for 4-threaded and 8-threaded workloads respectively was also observed.

EvtGen — recent developments and prospects

EvtGen is an event generator specialised for decays of heavy hadrons. Since its early development in the 90’s, the generator has been extensively used and has become an essential tool for heavy-flavour physics analyses. Throughout this time, its source code has remained mostly unchanged, except for additions of new decay models. In view of the upcoming boom of multi-threaded processing, we have launched a modernisation campaign with the chief goal of making EvtGen thread safe. We report on the challenges encountered in this endeavour and the milestones reached so far.

An Improved Dynamic Slicing Algorithm to Prioritize a Concurrent Multi-threading in Operating System

One of the issues with multi-threading in operating systems is the concurrency of operations or threads. In a multithreaded process on a single processor, the processor can switch execution resources between threads, enabling concurrent execution. Concurrency indicates that more than one thread is making progress, but the threads are not actually running simultaneously. The switching between threads occurs rapidly enough that the threads might appear to run simultaneously. In this paper, three related strategies for prioritizing multi-threading are presented: ACE-thread, Semaphore coprocessor, and the Concurrent Priority Threads Algorithm. The aim of this work is to enhance an existing prioritization algorithm, specifically the Concurrent Priority Threads Algorithm, by extending a dynamic slicing algorithm to prioritize multi-threading concurrently. The algorithm is designed to compute correct slices in multi-threading prioritization scenarios. Threads with the same highest priority can perform in a synchronized manner without encountering deadlocks. The C++ programming language is used to implement the extended algorithms. The improved algorithm achieved results that were 3% more accurate than the existing one. The outcomes of this work would facilitate the simultaneous execution of threads with the same priority, ultimately reducing waiting and processing times.

REAL-TIME SMOKE DETECTION IN VIDEO

The paper considers algorithmic and software for early fire detection based on smoke detection from video sequences
 generated by a static video camera. To detect areas with smoke, an algorithm has been developed that allows
 you to select such areas on video frames that are characterized by a number of features: the presence of a stable
 directional movement, compliance with the color characteristics of smoke, and a decrease in the energy value of highfrequency
 components relative to the background model. The feature of the algorithm is a step-by-step spatiotemporal
 analysis of candidate areas, which provides satisfactory computational costs and real-time operation
 on modern computing tools for high-resolution video frames. The algorithm is implemented using the functions
 of the OpenCV computer vision library and multi-threaded processing. The features and main functionality of the software
 implemented as a stationary application are given. The results of experimental studies on the evaluation
 of the efficiency of the algorithm and its speed are presented.

Intelligent Thread-Specific Rename Register Allocation for Simultaneous Multi-Threading Processors Based on Cache Behavior

Intelligent Thread-Specific Rename Register Allocation for Simultaneous Multi-Threading Processors Based on Cache Behavior

A Multithreaded Algorithm for the Computation of Sample Entropy

Many popular entropy definitions for signals, including approximate and sample entropy, are based on the idea of embedding the time series into an m-dimensional space, aiming to detect complex, deeper and more informative relationships among samples. However, for both approximate and sample entropy, the high computational cost is a severe limitation. Especially when large amounts of data are processed, or when parameter tuning is employed premising a large number of executions, the necessity of fast computation algorithms becomes urgent. In the past, our research team proposed fast algorithms for sample, approximate and bubble entropy. In the general case, the bucket-assisted algorithm was the one presenting the lowest execution times. In this paper, we exploit the opportunities given by the multithreading technology to further reduce the computation time. Without special requirements in hardware, since today even our cost-effective home computers support multithreading, the computation of entropy definitions can be significantly accelerated. The aim of this paper is threefold: (a) to extend the bucket-assisted algorithm for multithreaded processors, (b) to present updated execution times for the bucket-assisted algorithm since the achievements in hardware and compiler technology affect both execution times and gain, and (c) to provide a Python library which wraps fast C implementations capable of running in parallel on multithreaded processors.

The LHCb HLT2 Storage System: A 40-GB/s System Made of Commercial Off-the-Shelf Components and Open-Source Software

The LHCb (Large Hadron Collider beauty) experiment is designed to study differences between particles and anti-particles as well as very rare decays in the charm and beauty sector of the standard model at the LHC. With the major upgrade done in view of Run 3, the detector will read-out all events at the full LHC bunch-crossing frequency of 40 MHz. The LHCb data acquisition system will be subject to a considerably increased data rate, reaching a peak of 40 Tb/s. The second stage of the two-stage filtering consists of more than 10000 multi-threaded processes which simultaneously write output files at an aggregated band-width of 100 Gb/s. At the same time, a small number of file-moving processes will read files from the same storage to copy them over to tape-storage. This whole mechanism must run reliably over months and be able to cope with significant fluctuations. Moreover, for cost reasons, it must be built from off-the-shelf components. In this paper we describe LHCb’s solution to this challenge. We show the design, present reasons for the design choices, the configuration and tuning of the adopted software solution, and present performance figures.

Tamper-proof access control for IoT clouds using enclaves

Internet of Things (IoT) devices rely on cloud computing for processing user-sensitive data, like health recordings and geolocalization. In this case, security primitives like cryptography and certificate-based authentication does not prevent the cloud provider from acting against the privacy policy. This paper presents a framework for clouds to execute arbitrarily complex processing tasks over IoT data while maintaining the access control policies over the client’s control. We rely on a memory enclave to enforce that the cloud follows personal and customizable access policies and analyzed the security properties of our scheme. The performance evaluation reveals that these robust security improvements come with a latency overhead of just 0.1 ms, confirming the system’s viability. The system leverages multi-threaded processing inside an enclave to process thousands of client messages per second, achieving high scalability. This work also contributes with a microbenchmark that identifies how much each step of an enclave application influences the performance and evaluates the enclave viability for performing realistic IoT data processing.

Multi-subpopulation parallel computing genetic algorithm for the semiconductor packaging scheduling problem with auxiliary resource constraints

When the scheduling is established in a semiconductor packaging factory, frequent machine-related changes can pose a serious problem because of the large number of products processed using different machines with auxiliary resources. Thus, the efficiency of the scheduling algorithm is crucial for addressing the semiconductor packaging scheduling problem (SPSP). This study proposed a novel multi-subpopulation parallel computing genetic algorithm (MSPCGA) to solve the SPSP under practical production constraints. The MSPCGA uses a multithreaded central processing unit to perform parallel computing. The graphics processing unit (GPU) grid computing method was applied to modify the genetic algorithm computing architecture to increase the efficiency of the algorithm. Finally, the proposed MSPCGA outperformed two other metaheuristic algorithms in 12 evaluation scenarios. Additionally, the existing factory method was compared with the proposed MSPCGA to verify the effectiveness of the algorithm in practical applications.

Demonstration of ITER Real-Time Framework with application of PF coil control in KSTAR

ITER Real-Time Framework (RTF) is a middleware for developing fast real-time control applications such as plasma control system (PCS). In this framework, applications are built by creating and assembling Function Blocks (FBs) as atomic components of the application. The RTF can easily configure the application to be operated with multi-thread, multi-process, or multi-node processing under real-time mode. In this paper, we demonstrated capability of the RTF on the Poloidal Field (PF) coil Magnetic Power Supply (MPS) system of KSTAR. First, we fully implemented the KSTAR PF coil control logic from the KSTAR PCS into an independent RTF application. By configuring the real-time mode and multi-thread processing, 11 PF coils can be simultaneously controlled with a 20 KHz execution cycle. Second, we applied a built-in exception handler in the RTF to implementing protection from specified off-normal events such as PF Power Supply Fault (PSF) and PF OverCurrent Fault (OCF). Third, we integrated the standard real-time network interfaces of the KSTAR, the Reflective Memory (RFM) network, with the RTF application. Finally, we made a shot automation interface in order to run the RTF application according to the KSTAR shot sequence stages. This interface also has a snapshot functionality to store and load all experimental parameters for each shot number. We evaluated the effectiveness of the RTF application through a single PF MPS test connected with a 40 mH dummy load coil.

Fargraph+: Excavating the parallelism of graph processing workload on RDMA-based far memory system

Disaggregated architecture brings new opportunities to memory-consuming applications like graph processing. It allows one to outspread memory access pressure from local to far memory, providing an attractive alternative to disk-based processing. Although existing works on general-purpose far memory platforms show great potentials for application expansion, it is unclear how graph processing applications could benefit from disaggregated architecture, and how different optimization methods influence the overall performance.In this paper, we take the first step to analyze the impact of graph processing workload on disaggregated architecture by extending the GridGraph framework on top of the RDMA-based far memory system. We propose Fargraph+, a system with parallel graph data offloading and far memory coordination strategy for enhancing efficiency of graph processing workload on RDMA-based far memory architecture. Specifically, Fargraph+ reduces the overall data movement through a well-crafted, graph-aware data segment offloading mechanism. In addition, we use optimal data segment splitting and asynchronous data buffering to achieve graph iteration-friendly far memory access. We further configure efficient parallelism-oriented control to accelerate performance of multi-threading processing on graph iterations while improving memory efficiency of far memory access by utilizing RDMA queue features. We show that Fargraph+ achieves near-oracle performance for typical in-local-memory graph processing systems. Fargraph+ shows up to 11.2× speedup compared to Fastswap, the state-of-the-art, general-purpose far memory platform.

A Real-Time Recursion Correction Hybrid Linear State Estimator Using Stream Processing

This study intends to improve the accuracy, efficiency, and timeliness of state estimation (SE) for large-scale electric power systems by presenting a recursion correction hybrid linear state estimator that utilizes all the field measurements received from supervisory control and data acquisition (SCADA) systems and phasor measurement units (PMUs). We present a novel reformulation of the SE problem, where the SCADA and PMU measurements are processed asynchronously. Here, the PMU measurements along with the previous SE results are utilized during the time gap between two successive SCADA measurement sets to run a recursion correction, and thereby, provide real-time updates of the system state estimates. Moreover, the efficiency of this process is guaranteed through multithreaded stream processing. The effectiveness of the proposed method is demonstrated based on simulations involving IEEE 14-bus, 118-bus, and Polish 2383-bus systems.

3D Autonomous Surgeon’s Hand Movement Assessment Using a Cascaded Fuzzy Supervisor in Multi-Thread Video Processing

The purpose of the Fundamentals of Laparoscopic Surgery (FLS) training is to develop laparoscopic surgery skills by using simulation experiences. Several advanced training methods based on simulation have been created to enable training in a non-patient environment. Laparoscopic box trainers-cheap, portable devices-have been deployed for a while to offer training opportunities, competence evaluations, and performance reviews. However, the trainees must be under the supervision of medical experts who can evaluate their abilities, which is an expensive and time-consuming operation. Thus, a high level of surgical skill, determined by assessment, is necessary to prevent any intraoperative issues and malfunctions during a real laparoscopic procedure and during human intervention. To guarantee that the use of laparoscopic surgical training methods results in surgical skill improvement, it is necessary to measure and assess surgeons' skills during tests. We used our intelligent box-trainer system (IBTS) as a platform for skill training. The main aim of this study was to monitor the surgeon's hands' movement within a predefined field of interest. To evaluate the surgeons' hands' movement in 3D space, an autonomous evaluation system using two cameras and multi-thread video processing is proposed. This method works by detecting laparoscopic instruments and using a cascaded fuzzy logic assessment system. It is composed of two fuzzy logic systems executing in parallel. The first level assesses the left and right-hand movements simultaneously. Its outputs are cascaded by the final fuzzy logic assessment at the second level. This algorithm is completely autonomous and removes the need for any human monitoring or intervention. The experimental work included nine physicians (surgeons and residents) from the surgery and obstetrics/gynecology (OB/GYN) residency programs at WMU Homer Stryker MD School of Medicine (WMed) with different levels of laparoscopic skills and experience. They were recruited to participate in the peg-transfer task. The participants' performances were assessed, and the videos were recorded throughout the exercises. The results were delivered autonomously about 10 s after the experiments were concluded. In the future, we plan to increase the computing power of the IBTS to achieve real-time performance assessment.

Virtualization Airborne Trusted General Computing Technology

Aircraft information service systems, such as airborne information systems, airborne integrated maintenance management systems, and cabin management systems, have greatly improved the ease of use and maintenance of civil aircraft. The current computing platforms used for accommodating these systems are unable to satisfy the multifaceted requirements of future information-based aircraft, such as energy conservation, emission reduction, high-performance computing, and information security protection, due to their high computing capacity, weight, and power consumption. Based on multi-core multi-threaded processors, a security hardware unit with microkernel virtualization technology and a virtualization airborne trusted general computing service architecture is proposed, and key technologies, including a high-performance processing and high-security hardware unit, virtualization management software unit, and virtualization security protection architecture were designed. By building a verification environment, the proposed platform was verified in terms of its application accommodation function, platform performance, and network security protection, for comparison with the existing platforms. The results showed that our method can fulfill the requirements of these technical indicators and is applicable, not only to new-generation civil aircraft, but also to unmanned aerial vehicles (UAVs) and emergency rescue aircraft with high-performance safety-critical computing needs.

Наблюдение Аристотеля об иллюзии последействия движения в современном знании о восприятии времени и движения

In his work De Insomniis, Aristotle pointed out that after observing motion, objects at rest appeared to move. In modern literature, this effect, called the "waterfall illusion" or "the motion aftereffect", is widely researched and explained both scientifically and philosophically. Most researchers consider in the first place why this happens and what it means. This allows us to put forward new hypotheses and argue in favor of existing theories, in particular, thanks to the waterfall illusion, a hypothesis about multi-threaded data processing by neurons was proposed and some features of the work of adaptive perception mechanisms were demonstrated. At the same time, the implicit and unreasoned choice of a specific method of explanation to assert the advantages of a certain model while neglecting other empirical experience may be a methodological error, which can be seen in the example of S. Prosser's concept of dynamic frames.