Multi-stage Topology Research Articles

LSTM Multi-Stage Transfer Learning for Blood Pressure Estimation Using Photoplethysmography

Considerable research has been devoted to developing machine-learning models for continuous Blood Pressure (BP) estimation. A challenging problem that arises in this domain is the selection of optimal features with interpretable models for medical professionals. The aim of this study was to investigate evidence-based physiologically motivating features based on a solid physiological background of BP determinants. A powerful and compact set of features encompassing six physiologically oriented features was extracted in addition to another set of features consisting of six commonly used features for comparison purposes. In this study, we proposed a BP predictive model using Long Short-Term Memory (LSTM) networks with multi-stage transfer learning approach. The proposed model topology consists of three cascaded stages. First, a BP classification stage. Second, a Mean Arterial Pressure (MAP) regression stage to further approximate a quantity proportional to Vascular Resistance (VR) using the extracted Cardiac Output (CO) from the PPG signal. Third, the main BP estimation stage. The final stage (final BP prediction) is able to exploit embedded correlations between BP and the proposed features along with derived outputs carrying hemodynamic characteristics through the sub-sequence stages. We also constructed traditional single-stage Artificial Neural Network (ANN) and LSTM-based models to appraise the performance gain of our proposed model. The models were tested and evaluated on 40 subjects from the MIMIC II database. The LSTM-based multi-stage model attained a MAE ± SD of 2.03 ± 3.12 for SBP and 1.18 ± 1.70 mmHg for DBP. The proposed set of features resulted in drastic error reduction, of up to 86.21%, compared to models trained on the commonly used features. The superior performance of the proposed multi-stage model provides confirmatory evidence that the selected transferable features among the stages coupled with the high-performing multi-stage topology enhance blood pressure estimation accuracy using PPG signals. This indicates the compelling nature and sufficiency of the proposed efficient features set.

Design of bendable sandwich sheets with 3D printed CFRP cores via multi-stage topology optimization

The applications of sandwich structures are mainly limited to flat panel types due to their poor bendability. To develop bendable sandwich sheets, a new design strategy was proposed in this study, in which the density-based topology optimization was integrated with the multi-stage genetic algorithm (GA) to optimize the material layout so that the sandwich topologies can withstand potential failures including core shear failure, core-face sheet delamination and face buckling at given bending conditions. The topology optimization problem was mathematically formulated based on theoretically deduced failure constraints on core shear failure, face buckling and core-face sheet delamination. The adaptive multi-stage GA was adopted to solve the topology optimization problem with massive design variables and generate optimized topologies with sufficient resolutions to be additively manufacturable. The optimal topologies at given volume fraction constraints were additively manufactured using carbon fibre reinforced nylon (Onyx) and bending tests were conducted to check the bendability. Results indicate that topologically optimized SUS304/Onyx/SUS304 sandwich sheets can be bent without failure, which demonstrates the validity of the proposed topology optimization strategy. The proposed method is potentially capable of designing bendable sandwich sheets with arbitrary material combinations and is expected to expand the application envelope of lightweight sandwich structures.

Modeling of Conducted EM Emissions of Synchronous Buck Converters for Different Voltage Conversion Ratios

Large voltage conversion ratios of switching power converters operating at frequencies in the megahertz range are difficult to achieve because of the short pulses of the control signals for the transistor switches, and a multistage topology is a common solution to overcome this problem. A synchronous buck converter based on gallium-nitride FET switches is designed to analyze the effects of different voltage conversion ratios on the conducted electromagnetic (EM) emissions at the input of the converter. The input and output voltage and power levels are set to reproduce the operating conditions of the front-end and load converter in a multistage buck converter topology. The relationship between the generated conducted EM emissions and the voltage conversion ratio of the designed buck converter is approximated by the quadratic regression model. The synchronous buck converter with silicon transistor switches is designed to validate the proposed regression model. The extracted model allows accurate estimation of the conducted EM emissions generated by the buck converter for different voltage conversion ratios.

Application and practical validation of topology optimization technology for the frame of biaxial tensile testing machine

Biaxial tensile testing machines are used to improve accuracy of yield loci and constitutive model for sheet materials. The frame of these machines is the main load-bearing structure significantly affecting the machine accuracy. However, the available loading frames are too heavy to be practical for popularization and application. To reduce both the total weight of the frame and install consumption, this study develops a design method of stepwise multi-stage topology optimization based on the solid isotropic microstructures with penalization (SIMP) method. First, the validity of the finite element model during the optimization is verified by experiments. Next, the design method of stepwise multi-stage topology optimization is proposed based on the results of conventional topology optimization and the influence law of key parameters. This method is then applied to the topological optimization design of frames for a biaxial tensile testing machine. Finally, the optimized frame is manufactured, and biaxial tensile tests are conducted on the designed machine. The measurement of frame deformations shows that the frame weight is decreased by 19.5% compared with that of the initial design and that the frame stiffness meets design requirements. These results prove the effectiveness of the proposed method.

Multistage topology optimization of induction heating apparatus in time domain electromagnetic field with magnetic nonlinearity

Purpose The purpose of this paper is to solve efficiently the topology optimization (TO) in time domain problem with magnetic nonlinearity requiring a large-scale finite element mesh. As an actual application model, the proposed method is applied to induction heating apparatus. Design/methodology/approach To achieve TO with efficient computation time, a multistage topology is proposed. This method can derive the optimum structure by repeatedly reducing the design domain and regenerating the finite element mesh. Findings It was clarified that the structure derived from proposed method can be similar to the structure derived from the conventional method, and that the computation time can be made more efficient by parameter tuning of the frequency and volume constraint value. In addition, as a time domain induction heating apparatus problem of an actual application model, an optimum topology considering magnetic nonlinearity was derived from the proposed method. Originality/value Whereas the entire design domain must be filled with small triangles in the conventional TO method, the proposed method requires finer mesh division of only the stepwise-reduced design domain. Therefore, the mesh scale is reduced, and there is a possibility that the computation time for TO can be shortened.

Overview of Three-Stage Power Converter Topologies for Medium Frequency-Based Railway Vehicle Traction Systems

With new developments in power electronics and semiconductor devices, there has been an increasing interest in the adoption of power electronic traction transformer (PETT) topologies in railways, mainly for the purpose of mass and volume reduction against conventional topologies. Apart from traction transformers, examples include isolation circuits for on-board auxiliary power units (APU) and even 750 VDC, 110 VDC and lower voltage (e.g., 72 VDC) battery chargers. Special attention has been given to the more mature technology of three-stage (ac–dc–MFac–dc) configurations with intermediate medium frequency ac (MFac) links. In contrast to conventional architectures, it becomes difficult to select a suitable multistage topology of power electronics for the design of complex traction systems with advanced requirements. The power electronics utilized in different configurations have a significant effect on performance, efficiency, power quality (harmonics and stability), and cost indicators for the whole system, making the selection and design process more complex. The objective of this paper is to provide a clear overview of proposed topologies with special emphasis on the power electronic architectures utilized in three-stage PETT systems particularly for railway traction systems and on-board APUs. With regards to the listed range of possible architectures provided to the reader, key characteristics, such as total semiconductor (switches and diodes) count numbers per module per phase, input/output voltage levels, operating frequencies, and the most commonly used resonant networks, are summarized and discussed.

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration.

Trillium: A thermoacoustic-Stirling refrigerator implementation using an inline topology

To meet a small but growing demand for low global-warming potential refrigeration technologies, a thermoacoustic-Stirling refrigerator has been developed that uses helium as the working gas. Using a new multi-stage topology [Backhaus and Keolian, “In-line stirling energy system,” US patent 7,908,856 B2 (2011)], Trillium employs a collinear stack of three linear motors driven by voltage signals phased 120 degrees apart from one another. Above each motor is a thermal core that is comprised of a pair of novel aluminum microchannel heat exchangers on either side of a rolled Kapton® regenerator. The heat exchangers have an equivalent pore size of about a thermal boundary layer thicknesses that allows high effectiveness. The linear motors drive an acoustic wave that travels along the length of the machine. Taken in isolation, each thermal core and the motor-driven piston above and below (sealed using novel plastic flexure seals) forms a single alpha-Stirling machine; taken together Trillium is three Stirling machines working together with, in principle, zero vibration due to a stationary center-of-mass as a result of the motor phasing. The talk will explain the design and present performance measurements. [Work generously sponsored the Advanced Research Project Agency—Energy (ARPA-E) under their BEETIT program.]

Extending the bandwidth of low‐noise microwave amplifier through digital assist

The 3 dB bandwidth of a low-noise amplifier (LNA) is increased by 23% from a range of 1–6.7 GHz to a range of 1–8.25 GHz through digital assist. The LNA has a multi-stage topology and the gate bias voltages are dynamically optimised in real-time to obtain the best gain and noise figure as a function of the signal input frequency.

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A 0.13-μ m CMOS test-chip validates the feasibility and efficiency of the proposed design. Experimental results show that the proposed on-chip network achieves 1.9× to 8.2× reduction of silicon overhead compared to other design approaches.

Research on the MPPT Stability of the Single-Stage and Single-Phase Photovoltaic Grid-Connected System

At present the multi-stage transformation topology are more used in photovoltaic (PV) grid-connected system, although the control of this structure is relatively simple but the conversion efficiency is difficult to improve due to increase in transformation series. The single stage topology has a simple topology with high reliability and efficiency because of low power consumption, but control algorithm is more complex because of its power convert main circuit without DC-DC. This paper describes a method for maximum power point tracking (MPPT) in the single-stage and single-phase PV grid-connected system. In the paper, the nonlinear output characteristics of the PV including I-V & P-V are obtained in changed solar insulations or temperature based on MATLAB, and the MPPT algorithm which is based on the particle swarm optimization (PSO) method is also described. The simulation model of the single-stage and single-phase PV grid-connected system is built , and simulation results show the MPPT algorithm has excellent dynamic and static performances ,which verifies the PSO method is effective for MPPT in the single-stage and single-phase PV grid-connected system.

Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications

This letter proposes the design of a low group delay ultra-wideband (UWB) power amplifier (PA) in CMOS technology. The PA design employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of , and low group delay variation of . A resistive shunt feedback technique is adopted at the first stage of the amplifier to achieve good input matching, which controls the upper frequency of the UWB system. The third stage realizes the gain at the lower corner frequency and the second stage is used to smooth the flatness of the gain curve. By using this method, the proposed design has the lowest group delay variation among the recently reported CMOS PAs for 3.1 to 10.6 GHz applications.

Realisation of a single-chip, silicon germanium:C-based power amplifier for multi-band worldwide interoperability for microwave access applications

A fully integrated multi-band power amplifier (PA) using a 0.25 µm silicon germanium (SiGe):C process with an output power of above 25 dBm is presented. The behaviour of the amplifier has been optimised for multi-band operation covering, 2.4, 3.6 and 5.4 GHz (ultra wide band-worldwide interoperability for microwave access) frequency bands for higher 1-dB compression point and efficiency. Multi-band operation is achieved using a multi-stage topology where parasitic components of active devices are also used as components for matching networks, in turn decreasing the value and number of matching components. Measurement results of the PA provided the following performance parameters: 20.5 dBm 1-dB compression point, 23 dB gain and 7% efficiency at the 2.4 GHz band; 25.5 dBm 1-dB compression point, 31.5 dB gain and 17.5% efficiency at the 3.6 GHz band; 22.4 dBm 1-dB compression point, 24.4 dB gain and 9.5% efficiency at the 5.4 GHz band. Measurement results show that usage of both multi-stage topology and parasitic components as part of the matching network have provided a wider band operation with higher output power levels, above 25 dBm, with SiGe:C process.

Video Error Concealment by Integrating Greedy Suboptimization and Kalman Filtering Techniques

This paper addresses video error concealment techniques, focusing on motion vector recovery of P- and B-frames, to improve the decoded quality of videos when bit stream data incurs transmission errors. First, we propose a dynamic programming (DP) technique to optimize the path cost in a multistage topology and evaluate the goodness of boundary matching and side smoothness of recovered macroblocks. However, due to the high computational complexity of DP, a suboptimal alternative enhanced with an adaptive Kalman filtering algorithm is adopted instead. Experiments show that by considering the side smoothness between adjacent recovered MBs, the proposed algorithm improves the reconstructed video quality by about 0.4-0.9 dB with a packet loss rate up to 15%, compared to a traditional boundary matching algorithm. In addition, subjective image inspection demonstrates the efficiency of the proposed algorithm in retaining the continuity of lines and image details

An introduction to the multistage cube family of interconnection networks

The interconnection network in large-scale parallel/distributed supercomputer systems is a crucial component. Three networks are overviewed here. Multistage cube networks represent an important family of networks, which includes the omega, n-cube, multistage shuffle-exchange, delta, baseline, SW-banyan, and Generalized Cube. This family has been used or proposed for use in such systems as staran, pasm, Ultracomputer, the BBN Butterfly, the IBM RP3, and data-flow machines. The multistage cube topology, distributed routing control, and ability to be partitioned into independent subnetworks are examined. The Extra Stage Cube (ESC), a single-fault-tolerant multistage cube network, is described. The structure, control, and partitionability of the ESC, and how it functions when multiple faults occur, are presented. The Dynamic Redundancy (DR) network, a fault-tolerant multistage cube network that supports the incorporation of spare processors for fault tolerance, is discussed. Its structure, control, and partitionability into single-fault-tolerant subnetworks are explained.