Multistage Switching Networks Research Articles

Research on Scheduling Algorithm of Three-Stage Clos Switching Networks

The three-stage Clos switching network is a kind of multi-stage switching network which is commonly used to build a high-speed and large-capacity switching network, and the scheduling algorithm of the switching network affects the performance of the switching network. The article introduces and analyzes the research ideas of the scheduling algorithm of the three-stage Clos network, and provides a reference for further research on high-performance scheduling algorithms.

Quantitative Analysis of Multistage Switching Networks for Embedded Programmable Devices

This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size in the order of 1 KLUT, coupling flexibility with fast turn-around time. The non-blocking property for static connection of this class of MSSN is discussed. Our analysis shows pros and cons of adopting radix-2 or radix-4 MSSN structures, as well as the impact of bypass-paths to make the network fully hierarchical and locality-aware thanks also to a dedicated programming strategy. Implementation experiments carried out on STM CMOS 65 nm technology show the availability of various area-speed trade-offs, resulting in a range of ≃2× in frequency and a range of ≃ 4 × in area. Depending on the specific application-field, an optimal interconnect definition is thus achieved without compromising the routability properties. In this respect, the paper proposes a simplified application-driven model for evaluation of the best MSSN, including bypass-adoption and radix selection.

A Mathematical Theory for Multistage Battery Switching Networks

In this paper, we propose a mathematical theory for multistage battery switching networks. The theory aims to address several design issues in managing a large-scale battery system, including flexibility, reliability, efficiency, complexity (scalability) and sustainability. Our multistage battery switching network is constructed by a concatenation of various rectangular “shapes” of battery packs. The shape of each battery pack is specified by its voltage and its capacity. We show that our multistage battery switching network can support a maximum number of $L_{\max}$ loads under the constraint that the total voltages of these loads do not exceed a design constant $V_{\max}$ . Moreover, the voltage of each battery pack can be determined optimally by solving a Simultaneous Integer Representation (SIR) problem. To determine the capacity of each battery pack, we propose a max-min fairness battery allocation scheme, and show by computer simulations that such a scheme outperforms the uniform battery allocation scheme. We also propose a fault tolerant battery switching network that can still be operated properly even after $F_{\max}$ battery packs fail. Such a fault tolerant battery switching network enables a battery system to implement the Largest Remaining Capacity First (LRCF) policy that does not require the knowledge of the load profile.

Cross-Point Comparison of Multistage Non-Blocking Technologies

Multistage switching networks play important role in communication and computer network. They make communication nodes connect to each other. In computer hardware switches connect processors and memories. Initially, switches are arranged as one stage interconnection. As clients are growing, multistage is a must. The finding Clos multistage switching initiated multistage technologies. Benes improves Clos by reducing number of cross-points by using a 2 x 2 switch element and call re-routing. Batcher improves the technology by other way which is sorting destination address. Banyan is then joined to Batcher to simplify routing control. This paper analyses the number of cross-point required in Clos, Benes and Batcher Banyan to accomplish multistage switching architecture of 16, 64, 256, 1024 and 2048 input/output ports. As results, Clos cross-point is in averages 495.24% higher than Benes and 160.30% higher than Batcher Banyan. Clos blocking probabilities are closed to zero. Benes blocking probabilities are conditionally zero. Batcher Banyan blocking probabilities are zero.

Realization and Application of Large-Scale Fast Optical Circuit Switch for Data Center Networking

Applying optical switching to data center networks can greatly expand network bandwidth and reduce electrical power consumption, both of which are needed to meet the explosive traffic increase. The optical switch offers large bandwidth switching capability, and so eliminates the multistage switch network architecture needed with electrical switching. Furthermore, the single stage architecture of the optical switch greatly simplifies operating costs, which include cabling, while substantially reducing the number of transponders needed. Data center networks place very different demands on optical systems than communication networks. Grasping the right direction to proceed is of paramount importance. To realize the full potential of optical switches, such as scalability and cost effectiveness, we analyze the role of large-scale optical circuit switches and discuss the realization technologies that combine the two dimensions of space and wavelength. Our recent advances in large port-count optical switches are presented.

Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and area tradeoff since they are typically available as custom-designed hard macros. In this scenario, technology scaling is allowing designers to reduce the impact of the eFPGA area gap, while effective exploitation of all the technology options (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application needs. In this paper, we propose an look-up table-based soft-core eFPGA featuring a synthesizable and parametric architecture. A key point of our proposal is that we have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a significantly wide design-space available on very different technologies (we experimented STMicroelectronics CMOS 65 nm and BCD9s 0.11 $\mu \text{m}$ ). Application-driven evaluation showed how for a fixed eFPGA size (i.e., number of logic blocks) different configurations of the MSSN allow designers to speed up performance by 20/60%, as well as to maximize the computational density for a given area budget.

Modeling and Characterization of a Nonblocking $4\times 4$ Mach–Zehnder Silicon Photonic Switch Fabric

We present simulation and experimental results on a silicon photonic strictly nonblocking $4\times 4$ electrooptic Mach–Zehnder-based switch fabric. We propose a simulation framework based on the transfer matrix approach that enables calculating the transmission spectra of any type of multistage interconnect switch network. The model is used to analyze the spectral characteristics of the switch fabric. We also show experimental results on a fabric designed and fabricated in IBM's 90-nm photonics-enabled CMOS process. The fabric monolithically integrates the CMOS logic, the switch drivers, and all the photonics. We fully characterized all the transmittances of the switch and demonstrate onchip insertion loss between 1.5 and 3 dB and a crosstalk less than –25 dB for all the signal paths.

AWG-Based Non-Blocking Clos Networks

The three-stage Clos networks remain the most popular solution to many practical switching systems to date. The aim of this paper is to show that the modular structure of Clos networks is invariant with respect to the technological changes. Due to the wavelength routing property of arrayed-waveguide gratings (AWGs), non-blocking and contention-free wavelength-division-multiplexing (WDM) switches require that two calls carried by the same wavelength must be connected by separated links; otherwise, they must be carried by different wavelengths. Thus, in addition to the non-blocking condition, the challenge of the design of AWG-based multistage switching networks is to scale down the wavelength granularity and to reduce the conversion range of tunable wavelength converters (TWCs). We devise a logic scheme to partition the WDM switch network into wavelength autonomous cells, and show that the wavelength scalability problem can be solved by recursively reusing similar, but smaller, set of wavelengths in different cells. Furthermore, we prove that the rearrangeably non-blocking (RNB) condition and route assignments in these AWG-based three-stage networks are consistent with that of classical Clos networks. Thus, the optimal AWG-based non-blocking Clos networks also can achieve 100% utilization when all input and output wavelength channels are busy.

Modular Architectures of Multistage Switching Networks

This paper defines a procedure for designing the architecture of multistage switching networks. Our proposal is the result of a systematic study of the properties of multistage networks on one side and of optical switching systems on the other side. Modularity of the implementation is the primary concern, allowing the construction of a generic-size fabric by the simple cascading of multiple-stage modules. In this paper, we show in detail the application of the approach to a family of banyan networks, although the method can be extended to other types of networks. The designed architecture can be exploited for various implementation technologies, for instance, integrated optics and free-space optics. The method can even be applied to electronic VLSI/ULSI circuits. After presenting the design procedure, we discuss practical implementations in different technology scenar- ios. The main contribution of this paper is to simplify the building of large switches by cascading a number of switching modules that combine the internal stage architecture with the interconnection between stages.

Modelling of multiservice switching networks with overflow links for any traffic class

This study proposes a new analytical model of a multi-service switching network with overflow links with finite capacity in the first stage of the network. The proposed model assumes that overflow links can service a number of selected call classes from among all classes offered to the network. A particular attention is given to the method for a determination of the effective availability parameter for networks with overflow links. The proposed model can be also used to determine the dependence between the internal blocking probability and the capacity of overflow links. A relevant simulation study has confirmed high accuracy of the proposed method as well as the applicability of the model in engineering practice, in modelling of multi-stage switching networks both optical and electronic.

Universal Functional Block Design for All Purpose Network Realization in Multi-core System

while the last 30 years has seen the computer industry driven primarily by faster uni-processors those days have come to an end. Emerging in their place are multi processors containing multiple processor cores that are expected to exploit parallelism (3), (4). High reliability, availability and scalability (2)needs efficient multistage switching network to ensure performance (throughput) improvement. Current advancement in IC technology has helped us to design Universal Block for these different interconnection networks. Here in this paper we have designed a Universal Block for hypercube interconnection network using two different approaches indirect hypercube switching and shuffle exchange switching simultaneously. Index Terms: Universal Functional Block, Indirect Hypercube, Shuffle Exchange, Omega switching.

Optical Interconnection Bidirectional Data Vortex Network: Architecture and Performance Analysis

Data Vortex architecture is a unidirectional, highly scalable, all optical multistage interconnection packet switching network. In the present paper we propose Data Vortex architecture with bidirectional links in which the packets are routed both in the forward as well as in the reverse directions. The feasibility of data flow in both the directions is simulated in C environment. The performance analysis of bidirectional network is carried out and presented in terms of injection rate, latency and latency distribution. Finally, the comparison of the proposed bidirectional architecture with two Data Vortex networks connected in parallel for bidirectional operation is also presented.

First-Fit Scheduling for Multi-Stage Packet Switching Networks

We first propose a First-Fit Scheduling algorithm for a single stage interconnection network. We then classify multi-stage interconnection network in space, such as the 3-stage Clos network, when each spatial stage may allow time domain switching. We examine how scheduling could be performed for these stages for various combinations of space-time switching. The First-Fit algorithm is then extended to a three stage Clos network with scheduling in the first and third stage. Similar to other scheduling algorithms, full loading is achievable, while randomization of input selection is replaced by the use of arrival timing. This distributed algorithm applies to both cases of fixed length versus variable length packets. We simulated the performance for both cases. A case is made that for multi-gigabit per second link speed, variable length packets should be used to simplify scheduling and avoid fragmentation, with acceptable increase in delay.

Making the switch to SOAs

The first integrated multistage optical switch network has been fabricated and operated at a record speed of 160 Gbit/s. A team from the COBRA Research Institute at Eindhoven University of Technology in the Netherlands integrated several semiconductor optical amplifier (SOA) gates with low-loss passive components and wiring. This is a significant step towards an efficient and scalable means to create high connectivity reconfigurable networks. “The challenge has been threefold,” said Dr Kevin Williams, one of the researchers in the COBRA team. “Defining a highly functional circuit within a small footprint required that we miniaturised a number of circuit elements. A robust process technology was developed for the underlying active–passive integration. Finally, the combination of operating a sophisticated optical 160 Gbit/s de/multiplexer in combination with a complex unpackaged chip required considerable experimental care. We are now well placed to explore the operating limits for the circuit.”

On non-blocking multi-stage switching networks with rearrangement or repacking

This paper deals with recent results on non-blocking multi-stage switching networks with rearrangement or repacking and with simultaneous or sequential reswitching. Networks with rearrangement and simultaneous reswitching are considered in some detail. For networks with repacking and simultaneous reswitching, an efficient structure is suggested. For networks with rearrangement or repacking and sequential reswitching suitable configurations are presented. In addition to structure aspects, reswitching methods and crosspoint requirements are also considered.

Design alternatives for N-stage WDM optical planar permutation networks

Planar permutation networks are a class of multistage switching networks with no crossover between paths that interconnect switching elements. A well-known class of planar networks is the N−Stage network that provides a good compromise between the crossbar and the Benes network. In this paper, we address the problem of designing cost-effective N-Stage optical planar networks with space-wavelength switching capability. Such networks are used for switching in communication and computing systems that employ Wavelength Division Multiplexing (WDM) technology. We investigate two classes of space-wavelength N-stage planar networks, and for each class, we design a number of switching networks and analyze their hardware complexity. In addition, we propose a new method for designing a class of space-wavelength planar networks with reduced complexity. It is shown that, for F ≤ W (where F is the total number of fibers and W that of wavelengths) the proposed method results in planar networks with an average of 67% reduction in overall cost compared to that of networks based on fixed-range wavelength converters.

The enumeration method for selecting optimum switching network structures

In this paper it is shown that traditional continuous optimization methods for multistage switching networks may fail, leading to nonoptimal structures. Then, a simple enumeration method to solve the optimization problem is proposed. The numerical examples show that the parameters of optimum networks can be calculated very fast for any practical network sizes.

A class of multistage conference switching networks for group communication

There is a growing demand for network support for group applications, in which messages from one or more sender(s) are delivered to a large number of receivers. Here, we propose a network architecture for supporting a fundamental type of group communication, conferencing. A conference refers to a group of members in a network who communicate with each other within the group. We consider adopting a class of multistage networks, such as a baseline, an omega, or an indirect binary cube network, composed of switch modules with fan-in and fan-out capability for a conference network which supports multiple disjoint conferences. The key issue in designing a conference network is to determine the multiplicity of routing conflicts, which is the maximum number of conflict parties competing a single interstage link when multiple disjoint conferences simultaneously present in the network. Our results show that, for a network of size n /spl times/ n, the multiplicities of routing conflicts are small constants (between 2 and 4) for an omega network or an indirect binary cube network; while it can be as large as /spl radic/n/q + 1 for a baseline network, where q is the minimum allowable conference size. Thus, our design for conference networks is based on an omega network or an indirect binary cube network. We also develop fast self-routing algorithms for setting up routing paths in the newly designed conference networks. As can be seen, such an n /spl times/ n conference network has O(logn) routing time and communication delay and O(nlogn) hardware cost. The conference networks are superior to existing designs in terms of routing complexity, communication delay and hardware cost. The conference network proposed is rearrangeably nonblocking in general, and is strictly nonblocking under some conference service policy. It can be used in applications that require efficient or real-time group communication.

Multirate clos networks

Clos networks are a class of multistage switching network topologies that provide alternate paths between inputs and outputs, making it possible to minimize or eliminate the blocking that can otherwise occur in such networks. In his seminal paper in the Bell System Technical Journal in 1953, Charles Clos showed how these networks could be configured to make them nonblocking and effectively launched the systematic study of switching system performance, a field that has developed a rich technical literature, and continues to be very active and of continuing practical importance. This article describes how Clos' results have been generalized to systems that support connections with varying bandwidth requirements. These generalizations have extended the application of Clos networks well beyond their original technological context and have led to a number of interesting new results, especially in connection with systems that support multicast communication.

A general construction for nonblocking crosstalk‐free photonic switching networks

AbstractThe graph representation G(M) of a multistage switching network M is well known. Lea IEEE Trans Commun 38 (1990), 529–538 observed that link‐disjoint paths in M correspond to node‐disjoint paths in G(M). He proposed G(M) as a network by treating nodes as crossbars to transfer the node‐disjoint property to the crosstalk‐free property essential for photonic networks using directional couplers as components. However, such a network has its peculiarities and is not commonly used. In this paper, we will show how to take advantage of this correspondence to construct nonblocking crosstalk‐free networks using the vertical stacking method. Our construction simplifies the proofs of many existing results, as well as establishing some new results. © 2003 Wiley Periodicals, Inc.