Multi-rate Low-density Parity-check Research Articles

Construction of Multi-Rate Quasi-Cyclic LDPC Codes for Satellite Communications

To provide reliable transmissions with flexible rates for satellite communications, this paper presents a novel method of constructing multi-rate quasi-cyclic low-density parity-check (LDPC) codes. The basic idea is to generate low-rate codes from a high-rate mother code by combining shortening and extending, which ensures that the generated code family owns the same code length, in order to maintain the same frame structure. The code construction involves the design of base matrices and exponent matrices for the designed codes. A progressive row elimination and addition algorithm is proposed for designing the code base matrices from a high rate to low rates. This algorithm leads to the nested and systematic structure of the parity-check matrices, which are desirable for practical implementations of their encoders and decoders, while ensuring the optimal decoding thresholds. In addition, we construct a circulation coefficient matrix based on finite fields and select the optimal rows in this matrix to construct exponent matrices while considering of cycle structures. We demonstrate that the designed codes achieve better performance for all the code rates than the LDPC codes in DVB-S2X standards. In addition, the proposed codes do not exhibit error floors for their block error rates down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> .

A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS

This paper presents a frame-interleaved low-density parity-check (LDPC) decoder architecture with a new interconnect partitioning scheme and time-distributed Min-Sum decoding schedule. The architecture exploits the cyclic structure of the parity-check matrix by unrolling each check node update in time over all connected variable nodes in order to minimize wiring complexity and power. Multiple frames are interleaved to maximize hardware utilization, while coarse-grained clock gating is used to systematically turn off inactive logic and memories to save power. To demonstrate the scalability of the proposed architecture, a multirate LDPC decoder test chip was fabricated for the IEEE 802.11ad standard in the 28-nm CMOS technology node. The design occupies an area of 1.99 mm2, contains 160 Kb of embedded static random-access memory, and achieves a throughput of 6.78 Gb/s at 10 decoding iterations for all four code rates specified in the standard. With early decoding termination, the fabricated chip consumes between 104 and 279 mW of power at a target bit error rate of 10−6 under nominal operation at 0.9-V supply and 202-MHz clock rate, resulting in an energy efficiency between 1.53 and 4.12 pJ/bit/iteration. With clock-frequency and voltage scaling, the fabricated chip achieves an energy efficiency between 1.1 and 3.1 pJ/bit/iteration. This paper achieves the highest normalized energy efficiency among recently published CMOS-based decoders for the IEEE 802.11ad standard at nominal clock frequency and supply voltage.

A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes

In this paper, we present a low power multi-rate decoder hardware for low density parity check (LDPC) codes used in IEEE 802.11n wireless Local Area Network standard and we propose two novel techniques, sub-matrix reordering and differential shifting, for reducing the power consumption of a LDPC decoder hardware. The proposed hardware is a hybrid LDPC decoder and it implements layered min-sum decoding algorithm. The LDPC decoder hardware is implemented in Verilog HDL and it is verified to work correctly for all 12 block length and code rate combinations specified in the standard. We applied glitch reduction, sub-matrix reordering and differential shifting techniques to our multi-rate LDPC decoder hardware, and they reduced its power consumption on a Xilinx Virtex II FPGA by 25.93% on the average with a maximum reduction of 32.68% achieved for block length 648 and code rate 5/6. These techniques do not affect the bit error rate of a LDPC decoder hardware.

VLSI Design for Low-Density Parity-Check Code Decoding

Low-Density Parity-check (LDPC) code, being one of the most promising near-Shannon limit error correction codes (ECCs) in practice, has attracted tremendous attention in both academia and industry since its rediscovery in middle 1990's. Owning excellent coding gain, LDPC code also has very low error floor, and inherent parallizable decoding schemes. Compared to other ECCs such as Turbo codes, BCH codes and RS codes, LDPC code has many more varieties in code construction, which result in various optimum decoding architectures associated with different structures of the parity-check matrix. In this work, we first provide an overview of typical LDPC code structures and commonly-used LDPC decoding algorithms. We then discuss efficient VLSI architectures for random-like codes and structured LDPC codes. We further present layered decoding schemes and corresponding VLSI architectures. Finally we briefly address non-binary LDPC decoding and multi-rate LDPC decoder design.

Memory efficient multi-rate regular LDPC decoder for CMMB

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys¿ Design Compiler using Chartered 0.18 ¿m CMOS cell library. The synthesized design has the gate size of 455 K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

Implementation of a multi-rate and multi-size LDPC decoder

A fully reconfigurable architecture of a LDPC (low-density parity check) decoder for IEEE 802.11n system is proposed in this paper. This architecture can be operated in 12 kinds of modes specified in IEEE 802.11 system. Under the proposed architecture, memory usage and hardware complexity obviously improved, as compared with the other research works. Furthermore, the proposed decoder also able to support multi-rate and multi-size LDPC codes decoding. The proposed decoder was implemented in UMC 0.18µm CMOS technology. The maximum operating frequency is measured 200MHz and the corresponding power dissipation is 691.23mW and total area is 4.61mm2.

Error-resilient transmission of quality-scalable images over wireless channels

A new strategy for robust wireless transmission of scalable images is proposed. The proposed scheme utilizes the quality-progressive structure of the scalable code-stream and optimally protects different quality layers based on channel conditions using multi-rate low-density parity-check (LDPC) codes, leading to a flexible joint source-channel coding design. To accommodate optimal channel protection to important source layers, this novel technique is able to truncate the less important ones, when necessary. Furthermore, the number of iterations to find the optimal solution does not depend on the number of scalable source elements. Results show that the proposed scheme facilitates considerable gains in terms of subjective and objective quality as well as decoding probability of the retrieved images.

Code designs for cooperative communication

The goal of this article is to discuss the implementation of two cooperative protocols - decode-and-forward (DF) and estimate-and-forward (EF). In each case, the starting point is an information theoretic random coding scheme, which motivates a practical code construction. Low-density parity check (LDPC) codes are used as components in both protocols. In DF relaying, the problem boils down to a search for multi-rate LDPC codes that simultaneously perform well for the source-relay and the source- destination links. On the other hand, in EF relaying, the challenge is to design an efficient quantizer for forming a compressed estimate at the relay. The performance of each scheme is comparable to theoretical limits.

Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this paper, a 9-k code length multi-rate LDPC decoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 code mode, the regular 5/8 code mode, and the regular 7/8 code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10/sup -7/ at signal-to-noise ratio of 1.8 dB.