Parallel Multiprocessor System Research Articles

Modulus-based Synchronous Multisplitting Iteration Methods for an Implicit Complementarity Problem

AbstractWe construct modulus-based synchronous multisplitting iteration methods to solve a large implicit complementarity problem on parallel multiprocessor systems, and prove their convergence. Numerical results confirm our theoretical analysis and show that these new methods are efficient.

Reliability analysis of multilayer multistage interconnection networks

Multistage interconnection networks (MINs) play a key role in the performance of parallel computers and multiprocessor systems. A non-negligible demand on today's modern systems is to deliver multicast traffic. Therefore, design of efficient MINs that meets the routing requirement is vital. One of the main ideas to cope with this problem is the use of replicated MINs. However, one of the major concerns about these networks is the problem of unnecessary layer replication in the first stages, which recently proposes a new idea called multilayer MINs. Previous analyzes demonstrated that this new idea could lead to cost-effective topologies that had a very close performance to the replicated MINs in terms of throughput. Also, these analyzes indicate that these networks outperform replicated MINs in terms of delay. However, another critical parameter to prove the performance of most systems is reliability. Therefore, in this paper, we will focus on two essential parameters of cost and reliability to achieve both objectives; first, evaluating the performance of multilayer MINs in terms of reliability, second, to find the best topology among the multilayer MINs introduced in previous works in terms of cost-effectiveness (mean time to failure/cost ratio).

A wider convergence area for the MSTMAOR iteration methods for LCP

In order to solve large sparse linear complementarity problems on parallel multiprocessor systems, modulus-based synchronous two-stage multisplitting iteration methods based on two-stage multisplittings of the system matrices were constructed and investigated by Bai and Zhang (Numer. Algoritm. 62, 59-77 2013). These iteration methods include the multisplitting relaxation methods such as Jacobi, Gauss-Seidel, SOR and AOR of the modulus type as special cases. In the same paper the convergence theory of these methods is developed, under the following assumptions: (i) the system matrix is an H+-matrix and (ii) one acceleration parameter is greater than the other. Here we show that the second assumption can be avoided, thus enabling us to obtain an improved convergence area. The result is obtained using the similar technique proposed by Cvetkovic and Kostic (Numer. Linear Algebra Appl. 21, 534-539 2014), and its usage is demonstrated by an example of the LCP.

An Optimized Genetic Approach for Scheduling Task Duplication in Parallel Systems

Task Scheduling deals with the set of tasks assigned to parallel multiprocessor system and the execution order of the schedule so that the total execution time is minimized. The role of a good scheduling algorithm is to efficiently assign each task to a processor depending on the resources needed, the communication overhead between related tasks is reduced and the precedence relations among tasks are satisfied. It can be efficiently used for tasks that have a large calculation, and have time constraints to complete the schedule. The efficient execution of the task scheduling on parallel system takes the structure of the task and the performance characteristics of the proposed genetic algorithm. It falls in the category of NP-complete problem. This study proposes a parallel genetic algorithm-based approach to schedule tasks on parallel system with task duplication heuristics. Task duplication can minimize inter-processor communication and hence results in shorter finish times. Its performance is measured in comparison with the Round Robin (RR), First Come First Serve (FCFS), and Multi-level queue scheduling (MQS), Shortest Job First (SJF), Largest Job First (LJF) and Priority scheduling methods.

A new approach to improve reliability of the multistage interconnection networks

Because of their cost-effectiveness, multistage interconnection networks are widely used in parallel multiprocessor systems to make a connection among the processors and memory modules. One of the most important requirements for these communication systems is reliability. Adding a number of stages to these networks is one of the main approaches to promote this issue. Despite its modest cost and ease of implementation, this approach improves the reliability only to a small extent, which is not desirable, especially for large-scale systems. In this paper, we propose a new approach to improve reliability of the networks, called reducing nodes. Extensive reliability analyses from two major perspectives, terminal and broadcast, demonstrate that this idea can achieve a tremendous advantage over the aforementioned approach.

A Genetic-Fuzzy Algorithm for Load Balancing in Multiprocessor Systems

With the increasing use of computers in research contributions, added requirement for faster processing is now an important necessity. Parallel Processing describes the concept of running tasks which can be run simultaneously on several processors. Load balancing is very important problem in multiprocessor systems. In this paper, we introduce a approah based on Genetic Algorithms and Fuzzy Logic for laod balancing in parallel multiprocessor systems that call GAF algorithm. Extensive simulation shows our algorithm is better than other approach. Simualation results indicate our algorithm have maximum utilization and it reduce total response time of system. General Terms Scheduling, Genetic Algorithms, Fuzzy Logic.

AN EFFICIENT TASK SCHEDULING IN DISTRIBUTED COMPUTING SYSTEMS BY IMPROVED GENETIC ALGORITHM

Task Scheduling problem for heterogeneous systems is concerned with arranging the various tasks to be executed on various processors of a system so that computing resources are utilized most effectively. Parallel processing refers to the concept of speeding-up the execution of a task by dividing the task into multiple fragments that can execute simultaneously, each on its own processor i.e. it is the simultaneous processing of the task on two or more processors in order to obtain faster results. It can be effectively used for tasks that involve a large number of calculations, have time constraints and can be divided into a number of smaller tasks. The scheduling problem deals with the optimal assignment of a set of tasks onto parallel multiprocessor system and orders their execution so that the total completion time is minimized. An Optimal scheduling of parallel tasks with some precedence relationship, onto a parallel machine is known to be NP-complete. This precedence relationship among tasks can be represented as Directed Acyclic Graph (DAG). In this paper, a scheduling algorithm has been proposed to schedule DAG tasks on Heterogeneous processor which uses Genetic algorithm to get optimal schedule. The scheduling problem is also considered. This study includes a search for an optimal mapping of the task and their sequence of execution and also search for an optimal configuration of the parallel system. An approach for the simultaneous optimization of all these three components of scheduling method using genetic algorithm is presented and its performance is evaluated in comparison with the Min-Min and Max-Min scheduling methods.

Tasks Scheduling on Parallel Heterogeneous Multi-processor Systems using Genetic Algorithm

the increasing use of computers in research contributions, added need for faster processing has become an essential necessity. Parallel Processing refers to the concept of running tasks that can be run simultaneously on several processors. There are conditions that tasks have deadlines for scheduling. Therefore, the tasks should be scheduled before deadlines. May number of tasks before scheduling reached their deadline, Therefore, these tasks lost. These conditions are unavoidable. Thus, parallel multi-processor system tasks should be scheduled in a way, minimizing lost tasks. On the other hand, achieving good response times is necessary. this is an NP-Complete problem. In this article, we introduce a method based on genetic algorithms for scheduling tasks on parallel heterogeneous multi-processor systems for tasks with deadlines. The results of the simulations indicate reduced number of lost tasks in comparison with the LPT and SPT algorithms. Moreover, the response time of the proposed method due to its number of processing tasks, is appropriate, in comparison with the algorithm LPT and SPT.

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip

Runtime power management is a critical technique for reducing the energy footprint of digital electronic devices and enabling sustainable computing, since it allows electronic devices to dynamically adapt their power and energy consumption to meet performance requirements. In this article, we consider the case of MultiProcessor Systems-on-Chip (MPSoC) implemented using multiple Voltage and Frequency Islands (VFIs) relying on fine-grained Dynamic Voltage and Frequency Scaling (DVFS) to reduce the system power dissipation. In particular, we present a framework to theoretically analyze the impact of three important technology-driven constraints; (i) reliability-driven upper limits on the maximum supply voltage; (ii) inductive noise-driven constraints on the maximum rate of change of voltage/frequency; and (iii) the impact of manufacturing process variations on the performance of DVFS control for multiple VFI MPSoCs. The proposed analysis is general, in the sense that it is not bound to a specific DVFS control algorithm, but instead focuses on theoretically bounding the performance that any DVFS controller can possibly achieve. Our experimental results on real and synthetic benchmarks show that in the presence of reliability- and temperature-driven constraints on the maximum frequency and maximum frequency increment, any DVFS control algorithm will lose up to 87% performance in terms of the number of steps required to reach a reference steady state. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used. Nonetheless, we note that although conventional DVFS might become less effective with technology scaling, it will continue to play an important role in the context of emerging power management techniques, for example, for massively parallel multiprocessor systems where only a subset of cores can be turned on at any given point of time due to total power constraints.

A Novel Approach for Task Scheduling in Multiprocessor System

In multiprocessor system, scheduling of tasks to assigned on the number of processors. The major objective of task scheduling is to find minimum execution time of a program. It is well known that the complexity of a general scheduling problem is NP-Complete [9], there are number of heuristic have been developed. Each of which may either find optimal or near optimal scheduling under the different conditions. The task scheduling is represented by a directed acyclic graph (DAG). In this paper, we present a new scheduling algorithm which is called Task Scheduling based on Breath First Search(TSB). The TSB is queue based approach to schedule parallel tasks on the homogenous parallel multiprocessor system. Its performance is evaluated in comparison with Highest Level First with Estimate Time (HLFET) algorithm, Modified Critical Path (MCP) algorithm, Earliest Time First (ETF) algorithm and Dynamic Level Scheduling (DLS) algorithm in terms of Speedup, Efficiency, Load Balance and Normalized Scheduling Length (NSL).

Modulus-based synchronous two-stage multisplitting iteration methods for linear complementarity problems

In order to solve large sparse linear complementarity problems on parallel multiprocessor systems, we construct modulus-based synchronous two-stage multisplitting iteration methods based on two-stage multisplittings of the system matrices. These iteration methods include the multisplitting relaxation methods such as Jacobi, Gauss---Seidel, SOR and AOR of the modulus type as special cases. We establish the convergence theory of these modulus-based synchronous two-stage multisplitting iteration methods and their relaxed variants when the system matrix is an H ?+?-matrix. Numerical results show that in terms of computing time the modulus-based synchronous two-stage multisplitting relaxation methods are more efficient than the modulus-based synchronous multisplitting relaxation methods in actual implementations.

Modulus‐based synchronous multisplitting iteration methods for linear complementarity problems

SUMMARYBy an equivalent reformulation of the linear complementarity problem into a system of fixed‐point equations, we construct modulus‐based synchronous multisplitting iteration methods based on multiple splittings of the system matrix. These iteration methods are suitable to high‐speed parallel multiprocessor systems and include the multisplitting relaxation methods such as Jacobi, Gauss–Seidel, successive overrelaxation, and accelerated overrelaxation of the modulus type as special cases. We establish the convergence theory of these modulus‐based synchronous multisplitting iteration methods and their relaxed variants when the system matrix is an H + ‐matrix. Numerical results show that these new iteration methods can achieve high parallel computational efficiency in actual implementations. Copyright © 2012 John Wiley & Sons, Ltd.

Realization of the Detecting Method for Aircraft Digital Image Transmission System Based on Multi-Processor

The technologies of image block, pyramid and multi-threading were used in this program to design the high-speed image generation display module and the processes of image data scheduling and mapping and solve the problems of large-capacity image data modeling and high-speed displaying. The technology of direct digital frequency synthesis (DDS) was used to design the Doppler shifting signal generation module and the multi-processor parallel system architecture, which can analog the Doppler frequency shifting of the data communication signals and solve the problem of the authenticity of communication signals during the simulated flight.

Improved Task Scheduling on Parallel System using Genetic Algorithm

Parallel Processing refers to the concept of speeding-up the execution of a task by dividing the task into multiple fragments that can execute simultaneously, each on its own processor i.e. it is the simultaneous processing of the task on two or more processors in order to obtain faster results. It can be effectively used for tasks that involve a large number of calculations, have time constraints and can be divided into a number of smaller tasks. The scheduling problem deals with the optimal assignment of a set of tasks onto parallel multiprocessor system and orders their execution so that the total completion time is minimized. The efficient execution of the schedule on parallel multiprocessor system takes the structure of the application and the performance characteristics of the proposed algorithm. Many heuristics and approximation algorithms have been proposed to fulfill the scheduling task. It is well known NP-complete problem. This study proposes a genetic based approach to schedule parallel tasks on heterogeneous parallel multiprocessor system. The scheduling problem considered in this study includes next to search for an optimal mapping of the task and their sequence of execution and also search for an optimal configuration of the parallel system. An approach for the simultaneous optimization of all these three components of scheduling method using genetic algorithm is presented and its performance is evaluated in comparison with the First Come First Serve (FCFS), Shortest Job First (SJF), Round Robin (RR), Priority and Largest Job First (LJF) scheduling methods.

Scalable communication architectures for massively parallel hardware multi-processors

Modern complex embedded applications in multiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for highly-demanding applications. We demonstrated that in the massively parallel hardware multi-processors the communication network influence on both the throughput and circuit area dominates the processors influence, while the traditionally used flat communication architectures do not scale well with the increase of parallelism. Therefore, we propose to design highly optimized application-specific partitioned hierarchical organizations of the communication architectures through exploiting the regularity and hierarchy of the actual information flows of a given application. We developed related communication architecture synthesis strategies and incorporated them into our quality-driven model-based multi-processor design methodology and related automated architecture exploration framework. Using this framework we performed a large series of architecture synthesis experiments. Some of the results of the experiments are presented in this paper. They demonstrate many features of the synthesized communication architectures and show that our method and related framework are able to efficiently synthesize well scalable communication architectures even for the high-end massively parallel multi-processors that have to satisfy extremely stringent computation demands.

Modelling and performance evaluation of a novel internal-priority routing scheme for finite-buffered multistage interconnection networks

In this paper, the modelling, analysis and performance evaluation of a novel architecture for internal-priority finite-buffered multistage interconnection networks (MINs) are presented. We model the proposed architecture giving the details of its operation and describing its states and detailing conditions and effects of state transition; we also provide a formal model for evaluating its performance. The proposed architecture's performance is subsequently analysed under the uniform traffic condition, considering various offered loads, buffer lengths and MIN sizes, using simulations. We compare the internal-priority scheme vs. the non-priority (or single priority) scheme, by gathering metrics for the two most important network performance factors, namely, packet throughput and the mean time a packet needs to traverse the network. We demonstrate and quantify the improvements on MIN performance stemming from the introduction of priorities in terms of throughput and a combined performance indicator which depicts the overall performance of the MIN. These performance measures can be valuable assets for designers of parallel multiprocessor systems and networks in order to minimise the overall deployment costs and delivering efficient systems.

Pipelined On-Line Back-Propagation Training of an Artificial Neural Network on a Parallel Multiprocessor System

This work presents an on-chip learning of artificial neural networks in a FPGA multiprocessor system, where each neuron is implemented in a soft-core processor. In order to take maximum advantage of the distributed architecture, a pipelined version of the on-line back-propagation algorithm is used, providing a high degree of parallelism between neuron layers and, hence, a higher speed-up in relation to a sequential implementation.

Configuration of an optical waveguide interconnect mesh network based on EOPCB

An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board (EOPCB) with multimode polymer waveguide is proposed. The system consists of 22 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser (VCSEL)/positive intrinsic-negative (PIN) arrays are applied as the optical transmitters/receivers. Three 112 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 22 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.

Asynchronous multisplitting iteration with different weighting schemes

The multisplitting iteration method was presented by O’Leary and White [5] for solving large sparse linear systems on parallel multiprocessor system. In this paper, we further set up an asynchronous variant for the multisplitting iteration method with different weighting schemes studied by White [8]. Moreover, we establish a general convergence criterion for asynchronous iteration framework, and then prove the convergence of the new asynchronous multisplitting iteration method with different weighting schemes by making use of this general criterion.

New Algorithms for Permutation Passibility Behaviour of Some Irregular Multistage Interconnection Networks

There are many different ways to organize computational structures to exploit parallelism. Many research efforts around the world are being conducted with the purpose of determining hardware and software organizations that are best suited for general purpose parallel processing. In order to operate more efficiently a network is required to provide low latency and be able to handle large amount of traffic. Multistage Interconnection networks (MINs) play a vital role in the performance of these parallel multiprocessor systems. In multistage interconnection networks, the fixed interstate connections between adjacent stages exist with a number of switches at each stage that are dynamically set to establish the desired connections to route the requests from inputs to outputs. One very important parameter in measuring the performance of MINs is the permutation passability and the average path-length. The MINs can be Uniquepath or multi-path. The Unique-path MINs do not have fault tolerance at all. A multi-path MIN has fault-tolerance at each stage of the network. Also, It can easily be depicted from the construction of the Irregular networks that they are going to give better performance in terms of the average path length. For example in the best cases the source to destination path length in the Multi-path MIN the FT[2] is 2 and it is considerably more for the regular networks (3 or more, such as ASEN-2[3] it is 3). Therefore, FT is a strong candidate for such an analysis. Not many such studies have been reported in the literature. Therefore, new algorithms for the permutation passability of MDOT [1–2] and FT irregular MINs have been developed.