Multi-core FPGA Research Articles

Power quality assessment and power quality improvement in hospital facility

The power quality (PQ) assessment is carried out at a KIMS hospital facility by conducting the harmonic study as per IEEE3002.8 guidelines. As per PQ data obtained, the hospital facility is experiencing a significant number of PQ disturbances and violating IEEE519 limits for PQ in special application systems. It is found necessary to use a compensator for PQ improvement. A cost-effective compensator, DVR, is designed to improve PQ in the hospital facility. The designed DVR controller model is tested in the RT-LAB hardware-in-the-loop real-time simulation platform using OPAL-RT with multicore FPGA processors to validate the compatibility of the designed controller to be applied for real system implementation. Thus, PQ assessment helps in the appropriate design of compensating controllers to suit practicality. A comparative study of choice of designed DVR controllers such as PI, Fuzzy, ANN, ANFIS-PI optimised and ANFIS-Fuzzy optimised controllers tested in real-time for different cases and for different loading conditions are summarised.

Multithreading on reconfigurable hardware: a performance evaluation approach of a multicore FPGA architecture

Multithreading on reconfigurable hardware: a performance evaluation approach of a multicore FPGA architecture

NI P2P powered multi FPGA real-time data processing on tokamak diagnosis systems

On tokamaks, there are many diagnostics, which need real-time data acquisition and processing to provide useful information for plasma control. Some of the diagnostics required fast processing of multiple very high sampling rate signals. It is often difficult to achieve even with modern multi-core CPUs or GPUs. Moving large amount of data from the digitizers to the system ram will hurt the deterministic performance significantly. FPGA data pre-processing is a better choice when the data large and deterministic performance is required. When the task is too heavy for a single FPGA to implement, transfer large data between FPGAs is also required. On the polarimeter-interferometer diagnostics on J-TEXT, in order to calculate the density profile of the plasma in real-time, multiple chords of line-integrated density must be calculated first. The data acquisition system for the polarimeter-interferometer is equipped with 5 FlexRIO FPGAs, only one is acquiring the reference signal. Density calculation for every probing chord needs the reference signal. So this signal needs to be transferred to other FPGAs with strict real-time requirement. Mismatching a single sample, the result would be completely incorrect. NI P2P streaming allow the FPGA to transfer data without burdening the process. In the paper, the determinism characteristic and other performance of the P2P streaming is tested, and a mechanism to align local digitized samples with P2P streamed samples is presented. These results can be applied to other real-time data processing system that requires multiple FPGAs.

Rapid prototyping of Networks-on-Chip on multi-FPGA platforms

Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms.

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

A multicore FPGA platform with cache-integrated network interfaces (NIs) has been developed, appropriate for scalable multicores, that combine the best of two worlds - the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication). Furthermore, the proposed scheme provides virtualized user-level RDAM capabilities and special hardware primitives (counter, queues) for the communication and synchronization of the cores. This paper presents how the proposed architecture can be utilized in the domain of network processing applications using the hardware synchronization mechanisms. Two representatives network processing benchmarks are used; one for header processing and one for payload processing. The Multiple Reader Queue (MRQ) scheme is utilized in the case of header processing, while in the case of payload processing where transfer of bulk data is required, the user-level RDMA scheme is utilized. These applications are mapped and evaluated to an FPGA platform with up to 24 processors. The performance evaluation in the domain of network processing shows that the proposed scheme can offer low latency communication and increased programming efficiency while it also offloads the processor from the communication and synchronization processes.