Multicore Setting Research Articles

Applied static analysis and specialization of cross-core syscalls for multi-core AUTOSAR OS

The development of static real-time control systems often follows a closed-world assumption, allowing extensive RTOS-aware whole-program optimization. For single-core systems, previous work could show the high potential of control-flow-aware static system-call tailoring. However, due to an exponential state explosion in the analysis phase, it cannot simply be extended to a multi-core setting, since the core’s relative timing to each other is undetermined. In this work, we present MultiSSE, a multi-core capable and RTOS-aware static whole-system optimization. First, MultiSSE analyzes the system by determining the relative positions of multiple cores only when necessary. For that, it exploits structural control flow and optionally timing information to handle each core separately as much as possible. Based on the analysis result, a synthesis applies lock elision and system-call optimization to generate specialized multi-core real-time systems for AUTOSAR OS. To enable a static prediction of the run-time reduction, we additionally provide cost models for the optimized cross-core system calls and evaluate the approach with synthetic benchmarks and a real-world quadrotor application. MultiSSE was able to optimize or even completely elide costly cross-core system calls and system objects leading to a reduction of up to 14% of a task’s execution time. In this extended version of a conference publication (Entrup et al. 2023), we provide an advanced description, new cost models, and an end-to-end measurement by developing a synthesis complementing the analysis.

Robust Data-Driven Sparse Estimation of Distribution Factors Considering PMU Data Quality and Renewable Energy Uncertainty - Part II: Scalability and Applications

This two-part paper proposes a data-driven, robust, and scalable sparse estimation framework of distribution factors (DFs). Part I proposes a novel Adaptive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> -Lasso estimator with theoretically guaranteed robustness. For solving this estimator, common algorithms are not scalable to large-scale systems since they often fail to converge under parallelism. This is addressed in Part II, where a novel Online Parallel Stochastic Coordinate Descent algorithm with theoretically guaranteed scalability is proposed. It can simultaneously update massive DF estimates by stochastic parallelism with fast convergence. It also works recursively under a multi-core setting and does not need step-size tuning, which is applicable for cloud-computing-based online parallel estimation. Convergence bounds of this algorithm are theoretically proven, and its speedup and maximum parallel core number are derived. These guide practical computational resource allocation for high efficiency. The benefits of the framework are showcased in real-time market operations under locational marginal pricing (LMP) and financial transmission right (FTR) mechanisms for congestion management. Thanks to its sparsity-promoting effect, robustness, and scalability, it allows for correctly and fast solving LMPs, congestion patterns, and FTR revenues against uncertainties. Test results on IEEE 300- and European 9241-bus systems via Alibaba Cloud validate the high scalability of this algorithm and benefits of the proposed framework to system applications.

Learning-based Phase-aware Multi-core CPU Workload Forecasting

Predicting workload behavior during workload execution is essential for dynamic resource optimization in multi-processor systems. Recent studies have proposed advanced machine learning techniques for dynamic workload prediction. Workload prediction can be cast as a time series forecasting problem. However, traditional forecasting models struggle to predict abrupt workload changes. These changes occur because workloads are known to go through phases. Prior work has investigated machine-learning-based approaches for phase detection and prediction, but such approaches have not been studied in the context of dynamic workload forecasting. In this article, we propose phase-aware CPU workload forecasting as a novel approach that applies long-term phase prediction to improve the accuracy of short-term workload forecasting. Phase-aware forecasting requires machine learning models for phase classification, phase prediction, and phase-based forecasting that have not been explored in this combination before. Furthermore, existing prediction approaches have only been studied in single-core settings. This work explores phase-aware workload forecasting with multi-threaded workloads running on multi-core systems. We propose different multi-core settings differentiated by the number of cores they access and whether they produce specialized or global outputs per core. We study various advanced machine learning models for phase classification, phase prediction, and phase-based forecasting in isolation and different combinations for each setting. We apply our approach to forecasting of multi-threaded Parsec and SPEC workloads running on an eight-core Intel Core-i9 platform. Our results show that combining GMM clustering with LSTMs for phase prediction and phase-based forecasting yields the best phase-aware forecasting results. An approach that uses specialized models per core achieves an average error of 23% with up to 22% improvement in prediction accuracy compared to a phase-unaware setup.

FIMCE

Virtualization-based memory isolation has been widely used as a security primitive in various security systems to counter kernel-level attacks. In this article, our in-depth analysis on this primitive shows that its security is significantly undermined in the multicore setting when other hardware resources for computing are not enclosed within the isolation boundary. We thus propose to construct a fully isolated micro-computing environment (FIMCE) as a new primitive. By virtue of its architectural niche, FIMCE not only offers stronger security assurance than its predecessor, but also features a flexible and composable environment with support for peripheral device isolation, thus greatly expanding the scope of applications. In addition, FIMCE can be integrated with recent technologies such as Intel Software Guard Extensions (SGX) to attain even stronger security guarantees. We have built a prototype of FIMCE with a bare-metal hypervisor. To show the benefits of using FIMCE as a building block, we have also implemented four applications which are difficult to construct using the existing memory isolation method. Experiments with these applications demonstrate that FIMCE imposes less than 1% overhead on single-threaded applications, while the maximum performance loss on multithreaded applications is bounded by the degree of parallelism at the processor level.

Parallel local graph clustering

Graph clustering has many important applications in computing, but due to growing sizes of graph, even traditionally fast clustering methods such as spectral partitioning can be computationally expensive for real-world graphs of interest. Motivated partly by this, so-called local algorithms for graph clustering have received significant interest due to the fact that they can find good clusters in a graph with work proportional to the size of the cluster rather than that of the entire graph. This feature has proven to be crucial in making such graph clustering and many of its downstream applications efficient in practice. While local clustering algorithms are already faster than traditional algorithms that touch the entire graph, they are sequential and there is an opportunity to make them even more efficient via parallelization. In this paper, we show how to parallelize many of these algorithms in the shared-memory multicore setting, and we analyze the parallel complexity of these algorithms. We present comprehensive experiments on large-scale graphs showing that our parallel algorithms achieve good parallel speedups on a modern multicore machine, thus significantly speeding up the analysis of local graph clusters in the very large-scale setting.

Weighted-Tuple: Fast and Accurate Synchronization for Parallel Architecture Simulators

Computer architecture research relies on software simulation to evaluate processor performance. Single-threaded simulators have unacceptable simulation times when modeling complex architectures with hundreds of cores. While parallelizing a simulator can improve performance, parallel simulators face the issue of synchronizing threads, which forces them to trade performance for accuracy. We study relaxed synchronization policies for parallel architecture simulators and introduce the weighted-tuple synchronization policy. Weighted-tuple is a distributed synchronization scheme which improves upon existing policies. We evaluate weighted-tuple for two parallel simulator settings: multicore simulation and network-on-chip simulation. For the multicore setting using weighted-tuple synchronization, average simulation time is reduced by $8$ percent over barrier synchronization; error is also reduced by $28$ percent. For network-on-chip simulation, weighted-tuple synchronization improves simulation speed by $42$ percent with an $0.3$ percent error increase compared to the barrier baseline.

Rethinking serializable multiversion concurrency control

Multi-versioned database systems have the potential to significantly increase the amount of concurrency in transaction processing because they can avoid read-write conflicts. Unfortunately, the increase in concurrency usually comes at the cost of transaction serializability. If a database user requests full serializability, modern multi-versioned systems significantly constrain read-write concurrency among conflicting transactions and employ expensive synchronization patterns in their design. In main-memory multi-core settings, these additional constraints are so burdensome that multi-versioned systems are often significantly outperformed by single-version systems. We propose B ohm , a new concurrency control protocol for main-memory multi-versioned database systems. B ohm guarantees serializable execution while ensuring that reads never block writes. In addition, B ohm does not require reads to perform any bookkeeping whatsoever, thereby avoiding the overhead of tracking reads via contended writes to shared memory. This leads to excellent scalability and performance in multi-core settings. B ohm has all the above characteristics without performing validation based concurrency control. Instead, it is pessimistic, and is therefore not prone to excessive aborts in the presence of contention. An experimental evaluation shows that B ohm performs well in both high contention and low contention settings, and is able to dramatically outperform state-of-the-art multi-versioned systems despite maintaining the full set of serializability guarantees.

Four-Dimensional Gallant–Lambert–Vanstone Scalar Multiplication

The GLV method of Gallant, Lambert, and Vanstone (CRYPTO 2001) computes any multiple kP of a point P of prime order n lying on an elliptic curve with a low-degree endomorphism ? (called GLV curve) over $\mathbb{F}_{p}$ as $$kP = k_1P + k_2\varPhi(P) \quad\text{with } \max \bigl\{ |k_1|,|k_2| \bigr\} \leq C_1\sqrt{n} $$ for some explicit constant C 1>0. Recently, Galbraith, Lin, and Scott (EUROCRYPT 2009) extended this method to all curves over $\mathbb{F}_{p^{2}}$ which are twists of curves defined over $\mathbb{F}_{p}$ . We show in this work how to merge the two approaches in order to get, for twists of any GLV curve over $\mathbb{F}_{p^{2}}$ , a four-dimensional decomposition together with fast endomorphisms ?,? over $\mathbb{F}_{p^{2}}$ acting on the group generated by a point P of prime order n, resulting in a proven decomposition for any scalar k?[1,n] given by $$kP=k_1P+ k_2\varPhi(P)+ k_3\varPsi(P) + k_4\varPsi\varPhi(P) \quad \text{with } \max_i \bigl(|k_i| \bigr) 0. Remarkably, taking the best C 1,C 2, we obtain C 2/C 1<412, independently of the curve, ensuring in theory an almost constant relative speedup. In practice, our experiments reveal that the use of the merged GLV---GLS approach supports a scalar multiplication that runs up to 1.5 times faster than the original GLV method. We then improve this performance even further by exploiting the Twisted Edwards model and show that curves originally slower may become extremely efficient on this model. In addition, we analyze the performance of the method on a multicore setting and describe how to efficiently protect GLV-based scalar multiplication against several side-channel attacks. Our implementations improve the state-of-the-art performance of scalar multiplication on elliptic curves over large prime characteristic fields for a variety of scenarios including side-channel protected and unprotected cases with sequential and multicore execution.

ECMon

The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in techniques that use software speculation to better utilize the computational power of multicores. At the same time, several recent proposals for ensuring software reliability are not applicable in a multicore setting due to their inability to handle interprocessor shared memory dependences (ISMDs). The demands for performing speculation and ensuring software reliability in a multicore setting, although seemingly different, share a common requirement: the need for monitoring program execution and collecting interprocessor dependence information at low overhead. For example, an important component of speculation is the effcient detection of missspeculation which in turn requires dependence information. Likewise, tasks that help ensure software reliability on multicores, including recording for replay , require ISMD information. In this paper, we propose ECMon: support for exposing cache events to the software. This enables the programmer to catch these events and react to them; in effect, efficiently exposing the ISMDs to the programmer. In the context of speculation, we show how ECMon optimizes the detection of miss-speculation; we use this simple support to speculate past active barriers and achieve a speedup of 12% for the set of parallel programs considered. As an application of ensuring software reliability, we show how ECMon can be used to record shared memory dependences on multicores using no specialized hardware support at only 2.8 fold execution time overhead.

Migration policies for multi-core fair-share scheduling

In this paper, we describe an extension of the Linux kernel scheduler called the Practical Fair-Share Scheduler (PFS). PFS is a fair-share process scheduler designed to support real-time workloads with soft ( i.e. , elastic) timeliness requirements. Fair-share scheduling is a common choice for soft real-time systems since it is work conserving and ensures a minimum CPU allocation for each process. A novel aspect of PFS is its treatment of placement and migration in SMP or multi-core settings. Other fair-share schedulers have used ad hoc policies for handling these issues, often leading to underutilization and increased system lag. In contrast, PFS uses a strategy that maintains utilization without unfairly penalizing processes. We spend the remainder of this paper discussing placement and migration. A more extensive description of PFS, including source code, can be found at the download site listed in the citations.

Specialization of CML message-passing primitives

Concurrent ML (CML) is a statically-typed higher-order concurrent language that is embedded in Standard ML. Its most notable feature is its support for first-class synchronous operations . This mechanism allows programmers to encapsulate complicated communication and synchronization protocols as first-class abstractions, which encourages a modular style of programming where the underlying channels used to communicate with a given thread are hidden behind data and type abstraction.While CML has been in active use for well over a decade, little attention has been paid to optimizing CML programs. In this paper, we present a new program analysis for statically-typed higher-order concurrent languages that enables the compile-time specialization of communication operations. This specialization is particularly important in a multiprocessor or multicore setting, where the synchronization overhead for general-purpose operations are high. Preliminary results from a prototype that we have built demonstrate that specialized channel operations are much faster than the general-purpose operations.Our analysis technique is modular ( i.e., , it analyzes and optimizes a single unit of abstraction at a time), which plays to the modular style of many CML programs. The analysis consists of three steps: the first is a type-sensitive control-flow analysis that uses the program's type-abstractions to compute more precise results. The second is the construction of an extended control-flow graph using the results of the CFA. The last step is an iterative analysis over the graph that approximates the usage patterns of known channels. Our analysis is designed to detect special patterns of use, such as one-shot channels, fan-in channels, and fan-out channels. We have proven the safety of our analysis and state those results.

Multicore fibre laser phase locking by an external mirror

A theory of phase locking of radiation emitted byindividual fibres of a multicore fibre laser with the help of anexternal mirror is developed. The Talbot effect in radiationfrom an annular set of emitters is described analytically. Thetheoretical results are compared with the results of experiments and numerical calculations. The method of collectivemode selection in the multicore set with the help of a sphericalmirror producing a nearly concentric cavity is analysed.