Multi-core Platforms Research Articles

Efficient Parallelism of Post-Quantum Signature Scheme SPHINCS

SPHINCS was recently proposed as a stateless, quantum-resilient hash-based signature scheme. However, one possible limitation of SPHINCS is its signing speed, namely, the best known implementation merely produces a few hundred of signatures per second, which is not good enough, e.g., for a social website with a huge amount of users. Aiming at improving the singing throughput, we present highly parallel and optimized implementations of SPHINCS, which can be deployed on various multi-core platforms. As a first step, we give an elementary implementation on x86/64 processors, which proves the effectiveness and correctness of our implementations. To obtain a significantly higher throughput, we implement SPHINCS on Graphics Processing Units (GPUs). Furthermore, we develop a few general and hardware-specific techniques to take full advantage of the computing power of targeted platforms. We instantiate the underlying hash functions with three primitives. Our comprehensive benchmark shows that our work outperforms all the state-of-the-art implementations of SPHINCS regarding throughput with reasonable latency, and has scalability on multiple cores and multiple GPU cards. For instance, for the key generation algorithm instantiated with ChaCha running on a GeForce GTX 1080, we obtain 5152 signatures per second which is $7.88\times$ 7 . 88 × speedup faster than a recent FPGA implementation. When upgrade to TITAN Xp, 6,651 signatures are generated in one second. With four TITAN Xp GPUs, the obtained throughput satisfies vast majority scenarios.

Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey

Editor's notes: Multicore mobile processors have proliferated due to their efficiency in meeting the stringent performance requirement within a limited power budget. However, their continued success depends critically on managing their power and performance in the presence of dynamic workload variations. This article provides a survey of dynamic energy and thermal management approaches for multicore mobile platforms and discussed open challenges.

CCSDS-MHC on Raspberry Pi for Lossless Hyperspectral Image Compression

This paper is about Consultative Committee for Space Data System for Lossless Multispectral and Hyperspectral Image Compression (CCSDS-MHC) algorithm that is implemented on Raspberry Pi 3 Model B+ system using Open Multi-Processing (OpenMP). CCSDS-MHC algorithm along with the full prediction mode is opted due to its best compression ratio (CR) performance. The issue of Hyperspectral Image Compression is the loss of data when compress, thus CCSDS algorithm is used in this research. Besides, with current technologies that require low-power but high-performance devices, Raspberry Pi was chosen to be tested in terms of its performances while being compared to other platforms. AVIRIS (airborne) and Hyperion (spaceborne) are used to test the performance of the system. OpenMP is introduced to simplify the computational operation through parallelization to take advantage of the multi-core architecture of the hardware system. In term of execution time, CCSDS-MHC algorithm when parallelize using OpenMP gave the best performances about 69.4% for AVIRIS 1997 dataset, 69.3% for AVIRIS 2006 dataset and 67.7% for Hyperion dataset. The execution time of performance CCSDS-MHC in Raspberry Pi 3 Model B+ comparing with other different multicore platform is validate and the mean parallelize is measured. The result of comparison proves that faster performing task gives the best result due to higher speed of CPU-cores performances. From this research, it is proven that Raspberry Pi which is a low-power embedded platform able to compress the hyperspectral images at optimized speed with the implementation of OpenMP through CCSDS algorithm. Therefore, this research will be useful for further studies in lossless of hyperspectral images.

Implementation of High Performance EEG Based Seizure Detection And Analysis On Multicore Platform

About 50 million people worldwide suffer from epilepsy, the neurological disorder characterized by seizures. The primary tool for diagnosis of an epileptic seizure is an electroencephalography (EEG) which records the brain’s spontaneous electrical activity. This requires the placement of a minimum of 16 electrodes on the scalp with each electrode being interpreted as a channel. The classification of seizure detection and analysis techniques mainly work in two stages, where features are extracted from raw EEG data in the first stage and then the obtained features are used as input for the classification process in the second stage. Traditionally the Seizure detection algorithms were implemented using DSP Processor or FPGAs. But these single core platforms are constrained with respect to speed of operation and power consumption. There is a greater need to reduce the power consumption as well to increase the speed of EEG seizure detection system. This problem can be addressed using the Multicore Processors, which process data simultaneously. This project presents a high performance multicore platform for EEG based seizure detection and analysis. This platform performs continuous multichannel detection and analysis of seizures for epilepsy patients. The detection unit will detect the seizures based on feature extraction process once the seizure detection is done enables the analysis circuit that process the data based Uridva Triyabhakyam based 128 point FFT and transmits energy and frequency contents of EEG data. All proposed blocks are simulated and synthesized using Xilinx ISE and coding is done in Verilog.

Parallel resolution of large GNSS networks using carrier ranges

Owing to the increasing numbers of navigation satellites, available frequencies, and tracking stations, the computational efficiency of large GNSS networks has become a critical issue, especially when undifferenced (UD) pseudorange and carrier phase observations are used. By converting UD carrier phases into carrier ranges before implementing the integrated processing of a whole network, the UD calculation time can be greatly decreased. However, because a common multicore hardware platform is not fully utilized to optimize the algorithm, the processing of a whole network is still time consuming. In this paper, this problem is overcome by applying the multicore parallel computing technology, namely the Task Parallel Library (TPL). To improve the processing efficiency of large GNSS networks using UD carrier ranges and based on the task parallelism and data parallelism offered through TPL, the wide-lane (WL) and narrow-lane (NL) fractional cycle biases (FCBs), and carrier ranges are computed in parallel, and the integrated processing of a whole network is performed by establishing the normal equation in parallel and adopting parallel computing for Cholesky decomposition. The proposed strategy is validated using GPS, BDS and Galileo observation data recorded from January 6, 2019, to January 26, 2019 by the IGS network with a global distribution of approximately 500 stations. The average positioning accuracies in the east, north and vertical components are 2.54, 2.34 and 4.41 mm, respectively, and the average SDBS ambiguity fixing rate is 93.18%. The average time consumptions for step 1, 2 and 3 are reduced from 151.45, 248.80 and 44.35 min to 32.20, 52.71 and 14.25 min, respectively, with acceleration ratios of 4.70, 4.72 and 3.11 times, respectively, on a six-core platform.

Global Scheduling Real-Time Parallel Tasks on Multicore Platforms

Traditional real-time task scheduling strategies only considers cores scheduling, and do not take in account memory access and cache effects on multicore platforms. In this paper, we propose real-time parallel scheduling (PRTTS) strategy on multicore platforms. Each task is represented as a directed acyclic graph (DAG). The priorities of tasks are assigned according to task periods (rate monotonic, RM). In PRTTS scheduling strategy, priorities of tasks that access memory are promoted over priorities of tasks not accessing memory. Tasks accessing the data in the cache is dynamically raised to highest priority. The results of simulation experiment show that proposed new scheduling strategy offers better performance in terms of core utilization and schedulability rate of tasks.

Energy-Efficient Parallel Real-Time Scheduling on Clustered Multi-Core

Energy-efficiency is a critical requirement for computation-intensive real-time applications on multi-core embedded systems. Multi-core processors enable intra-task parallelism, and in this work, we study energy-efficient real-time scheduling of constrained deadline sporadic parallel tasks, where each task is represented as a directed acyclic graph (DAG). We consider a clustered multi-core platform where processors within the same cluster run at the same speed at any given time. A new concept named speed-profile is proposed to model per-task and per-cluster energy-consumption variations during run-time to minimize the expected long-term energy consumption. To our knowledge, no existing work considers energy-aware real-time scheduling of DAG tasks with constrained deadlines, nor on a clustered multi-core platform. The proposed energy-aware real-time scheduler is implemented upon an ODROID XU-3 board to evaluate and demonstrate its feasibility and practicality. To complement our system experiments in large-scale, we have also conducted simulations that demonstrate a CPU energy saving of up to 67 percent through our proposed approach compared to existing methods.

ReMap: Reliability Management of Peak-Power-Aware Real-Time Embedded Systems Through Task Replication

Increasing power densities in future technology nodes is a crucial issue in multicore platforms. As the number of cores increases in them, power budget constraints may prevent powering all cores simultaneously at full performance level. Therefore, chip manufacturers introduce a power budget constraint as Thermal Design Power (TDP) for chips. Meanwhile, multicore platforms are suitable for implementation of fault-tolerance techniques to achieve high reliability. Task Replication is a known technique to tolerate transient faults. However, careless task replication may lead to significant peak power consumption. In this paper, we consider the problem of achieving a given reliability target while keeping the total power consumption under the chip TDP for a set of periodic soft real-time tasks. For this purpose, we propose a method for mapping and scheduling periodic soft real-time tasks in multicore embedded systems. The proposed method consists of three phases: (i) Reliability-Aware Lowest Utilization Mapping, (ii) Maximum-Power-Aware EDF Scheduling, and (iii) Reliability-and-Peak-Power-Aware Dynamic-Voltage-Frequency-Scaling. Our experiments show that our proposed method provides up to 38.4% (on average by 25%) peak power reduction compared to state-of-the-art methods.

Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA

Matrix Factorization (MF) based on Stochastic Gradient Descent (SGD) is a powerful machine learning technique to derive hidden features of objects from observations. In this article, we design a highly parallel architecture based on Field-Programmable Gate Array (FPGA) to accelerate the training process of the SGD-based MF algorithm. We identify the challenges for the acceleration and propose novel algorithmic optimizations to overcome them. By transforming the SGD-based MF algorithm into a bipartite graph processing problem, we propose a 3-level hierarchical partitioning scheme that enables conflict-minimizing scheduling and processing of edges to achieve significant speedup. First, we develop a fast heuristic graph partitioning approach to partition the bipartite graph into induced subgraphs; this enables to efficiently use the on-chip memory resources of FPGA for data reuse and completely hide the data communication between FPGA and external memory. Second, we partition all the edges of each subgraph into non-overlapping matchings to extract the maximum parallelism. Third, we propose a batching algorithm to schedule the execution of the edges inside each matching to reduce the memory access conflicts to the on-chip RAMs of FPGA. Compared with non-optimized FPGA-based baseline designs, the proposed optimizations result in up to 60× data dependency reduction, 4.2× bank conflict reduction, and 15.4× speedup. We evaluate the performance of our design using a state-of-the-art FPGA device. Experimental results show that our FPGA accelerator sustains a high computing throughput of up to 217 billion floating-point operations per second (GFLOPS) for training very large real-life sparse matrices. Compared with highly-optimized GPU-based accelerators, our FPGA accelerator achieves up to 12.7× speedup. Based on our optimization methodology, we also implement a software-based design on a multi-core platform, which demonstrates 1.3× speedup compared with the state-of-the-art multi-core implementation.

A Novel Statistical Learning-Based Methodology for Measuring the Goodness of Energy Profiles of Applications Executing on Multicore Computing Platforms

Accurate energy profiles are essential to the optimization of parallel applications for energy through workload distribution. Since there are many model-based methods available for efficient construction of energy profiles, we need an approach to measure the goodness of the profiles compared with the ground-truth profile, which is usually built by a time-consuming but reliable method. Correlation coefficient and relative error are two such popular statistical approaches, but they assume that profiles be linear or at least very smooth functions of workload size. This assumption does not hold true in the multicore era. Due to the complex shapes of energy profiles of applications on modern multicore platforms, the statistical methods can often rank inaccurate energy profiles higher than more accurate ones and employing such profiles in the energy optimization loop of an application leads to significant energy losses (up to 54% in our case). In this work, we present the first method specifically designed for goodness measurement of energy profiles. First, it analyses the underlying energy consumption trend of each energy profile and removes the profiles that exhibit a trend different from that of the ground truth. Then, it ranks the remaining energy profiles using the Euclidean distances as a metric. We demonstrate that the proposed method is more accurate than the statistical approaches and can save a significant amount of energy.

A novel gateway-based solution for remote elderly monitoring.

Internet of Things (IoT) technologies have been applied to various fields such as manufacturing, automobile industry and healthcare. IoT-based healthcare has a significant impact on real-time remote monitoring of patients' health and consequently improving treatments and reducing healthcare costs. In fact, IoT has made healthcare more reliable, efficient, and accessible. Two major drawbacks which IoT suffers from can be expressed as: first, thelimited battery capacityof thesensorsis quickly depleted due to the continuous stream of data; second, the dependence of the system on the cloud for computations and processing causes latency in data transmission which is not accepted in real-time monitoring applications. This research is conducted to develop a real-time, secure, and energy-efficient platform which provides a solution for reducing computation load on the cloud and diminishing data transmission delay. In the proposed platform, the sensors utilize a state-of-the-art power saving technique known as Compressive Sensing (CS). CS allows sensors to retrieve the sensed data using fewer measurements by sending a compressed signal. In this framework, the signal reconstruction and processing are computed locally on a Heterogeneous Multicore Platform (HMP) device to decrease the dependency on the cloud. In addition, a framework has been implemented to control the system, set different parameters, display the data as well as send live notifications to medical experts through the cloud in order to alert them of any eventual hazardous event or abnormality and allow quick interventions. Finally, a case study of the system is presented demonstrating the acquisition and monitoring of the data for a given subject in real-time. The obtained results reveal that the proposed solution reduces 15.4% of energy consumption in sensors, that makes this prototype a good candidate for IoT employment in healthcare.

Efficient Open Source Software Radio on Heterogeneous Multicore Embedded Platforms

Software radio is a common technique in modern communications equipment, and it is frequently implemented using heterogeneous multicore processors because of its high computational requirements. Programming such systems is still a challenging task and developers rely often on standard parallel APIs and frameworks such as OpenMP and OpenCL. These tools, however, present some limitations when more than one algorithm has to be accelerated. The typical workload of a software radio usually includes several compute-intensive algorithms so it might be still better served by more specific tools, especially on embedded platforms. In this article, a development methodology for implementing software radio applications in heterogeneous multicore embedded platforms is proposed. The methodology is based on GNU radio, a free and open source software toolkit. To validate the methodology, a DVB–T receiver has been ported to an embedded heterogeneous multicore platform as a proof-of-concept. The results show that two different compute-intensive algorithms, Viterbi decoder, and FFT, can be simultaneously accelerated, improving the DVB–T receiver performance by 63%.

The search‐based scheduling algorithm HP* for parallel tasks on heterogeneous platforms

SummaryScheduling is a widely used method in parallel computing, which assigns tasks to compute resources of a parallel environments. In this article, we consider independent parallel tasks to be scheduled onto a heterogeneous execution platform consisting of a set of multicores of different architecture. Each parallel task has an internal potential parallelism which allows a parallel execution on any multicore processors. However, the execution time may differ due a different computation speed of different multicores. In this article, we propose a new search‐based scheduling algorithm Heterogeneous Parallel task scheduling based on A* (called HP*) to solve the problem of scheduling independent parallel tasks onto heterogeneous multicore platforms. Specifically, we propose a heuristic cost function needed for an informed search. Also, three pruning techniques are proposed, which are shown to significantly reduce the search space of HP*. Performance measurements on a heterogeneous platform are performed and the results of HP* are compared to scheduling results of other popular scheduling methods. The performance results with benchmark tasks from the SPLASH‐3 benchmark suite demonstrate the good scheduling results and the improvements achieved by HP*.

A Recursive Algebraic Coloring Technique for Hardware-efficient Symmetric Sparse Matrix-vector Multiplication

The symmetric sparse matrix-vector multiplication (SymmSpMV) is an important building block for many numerical linear algebra kernel operations or graph traversal applications. Parallelizing SymmSpMV on today’s multicore platforms with up to 100 cores is difficult due to the need to manage conflicting updates on the result vector. Coloring approaches can be used to solve this problem without data duplication, but existing coloring algorithms do not take load balancing and deep memory hierarchies into account, hampering scalability and full-chip performance. In this work, we propose the recursive algebraic coloring engine (RACE), a novel coloring algorithm and open-source library implementation that eliminates the shortcomings of previous coloring methods in terms of hardware efficiency and parallelization overhead. We describe the level construction, distance- k coloring, and load balancing steps in RACE, use it to parallelize SymmSpMV, and compare its performance on 31 sparse matrices with other state-of-the-art coloring techniques and Intel MKL on two modern multicore processors. RACE outperforms all other approaches substantially. By means of a parameterized roofline model, we analyze the SymmSpMV performance in detail and discuss outliers. While we focus on SymmSpMV in this article, our algorithm and software are applicable to any sparse matrix operation with data dependencies that can be resolved by distance-k coloring.

Supporting I/O and IPC via fine-grained OS isolation for mixed-criticality real-time tasks

Efforts towards hosting safety-critical, real-time applications on multicore platforms have been stymied by a problem dubbed the “one-out-of-m” problem: due to excessive analysis pessimism, the overall capacity of an m-core platform can easily be reduced to roughly just one core. The predominant approach for addressing this problem introduces hardware-isolation techniques that ameliorate contention experienced by tasks when accessing shared hardware components, such as DRAM memory or caches. Unfortunately, in work on such techniques, the operating system (OS), which is a key source of potential interference, has been largely ignored. Most real-time OSs do facilitate the use of a coarse-grained partitioning strategy to separate the OS from user-level tasks. However, such a strategy by itself fails to address any data sharing between the OS and tasks, such as when OS services are required for interprocess communication (IPC) or I/O. This paper presents techniques for lessening the impacts of such sharing, specifically in the context of $${\textsf {MC}}^{\textsf {2}}$$ , a hardware-isolation framework designed for mixed-criticality systems. Additionally, it presents the results from micro-benchmark experiments and a large-scale schedulability study conducted to evaluate the efficacy of the proposed techniques and also to elucidate sharing vs. isolation tradeoffs involving the OS. This is the first paper to systematically consider such tradeoffs and consequent impacts of OS-induced sharing on the one-out-of-m problem.

Parallel Computing and Multicore Platform to Assess Electric Vehicle Hosting Capacity

The impact generated by the massive connection of electric vehicles (EVs) in the distribution networks needs to be evaluated through methodologies that consider the stochastic behavior of the EV connections. These methodologies must allow obtaining representative results of annual simulations, considering different charging scenarios, with high resolution of time steps. This kind of analysis implies a combinatorial explosion of case studies with a high computational cost. This article presents a methodology aimed at reducing the simulation time required to determine the EV hosting capacity (HC), understood as the maximum EV penetration level that a distribution network could host before affecting its operating limits, through the co-simulation of hardware and software. Monte Carlo methods and quasi-static time series simulation concepts are used to model the connection features of EVs. The simulation and implementation are developed using parallel computing, and MATLAB and OpenDSS software. The methodology is tested on the IEEE 123 nodes system which shows the dependence of the HC indicator with the location and type EV chargers. Finally, the benefits of parallel computing in the proposed methodology are exposed to get a significant reduction in the execution time to evaluate the HC in the IEEE 123 nodes system.

Evaluation of memory performance in NUMA architectures using Stochastic Reward Nets

Understanding memory performance in multi-core platforms is a prerequisite to perform optimizations. To this end, this paper presents analytical models based on Stochastic Reward Nets (SRNs) to model and evaluate the memory performance of Non-Uniform Memory Access (NUMA) multi-core architectures. The approach considers the details of the architecture and first proposes a monolithic SRN model that evaluates the memory performance in terms of the mean memory response time. Since the monolithic model incurs a state space explosion with an increasing number of cores and memory controllers, two approximate models are presented that are able to evaluate large-scale NUMA architectures. The SRNs are validated through measurements on two NUMA multi-core platforms, a 64-core AMD Opteron server and a 72-core Intel system. The results demonstrate the ability of the proposed models to accurately compute the mean memory response time on NUMA architectures. The results also provide valuable information that runtime systems and application designers can use to optimize execution of parallel applications on such architectures.

Improving the Performance of Actors on Multi-cores with Parallel Patterns

The Actor-based programming model is largely used in the context of distributed systems for its message-passing semantics and neat separation between the concurrency model and the underlying hardware platform. However, in the context of a single multi-core node where the performance metric is the primary optimization objective, the “pure” Actor Model is generally not used because Actors cannot exploit the physical shared-memory, thus reducing the optimization options. In this work, we propose to enrich the Actor Model with some well-known Parallel Patterns to face the performance issues of using the “pure” Actor Model on a single multi-core platform. In the experimental study, conducted on two different multi-core systems by using the C++ Actor Framework, we considered a subset of the Parsec benchmarks and two Savina benchmarks. The analysis of results demonstrates that the Actor Model enriched with suitable Parallel Patterns implementations provides a robust abstraction layer capable of delivering performance results comparable with those of thread-based libraries (i.e. Pthreads and FastFlow) while offering a safer and versatile programming environment.

A Real-time Image Recognition System Based on Improved Jacintonet Convolutional Neural Network

With the emergence and development of new automation industries such as unattended supermarkets and smart picking orchards, the demand for real-time systems based on embedded platforms is increasing day by day. Heterogeneous multi-core processors are widely used in modern integrated circuit design due to their advantages of low power consumption and high parallelism. More and more real-time systems are implemented on heterogeneous multi-core platforms. Based on the heterogeneous multi-core embedded system, the network parameters and architecture of jacintonet model are improved, and a real-time system for fruit image recognition is realized by using the improved network. A small sample data set is used to train the modified network and the trained network is imported into the system for testing. The result shows that the improved jacintonet network can run well on heterogeneous multi-core system and has the same recognition performance as the original network.

A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.