Heterogeneous Integration Research Articles

Development of flip-chip technology for the optical drive of superconducting circuits

We discuss the flip-chip mounting process of photodiodes and fiber sleeves on silicon substrates to meet the increasing demand for fabrication of highly integrated and hybrid quantum circuits for operation at cryogenic temperatures. To further increase the yield and success rate of the flip-chip procedure, the size of the gold stud bumps, and flip-chip parameters were optimized. Moreover, to connect optical fibers to the photodiodes in an optimal position, the fiber sleeves were aligned with specially fabricated alignment circles before applying thermocompression with the flip-chip machine. The mounted photodiodes were tested at both room temperature and cryogenic temperature, and we find that mechanical imperfections of the sleeve-ferrule combination limit the overall alignment accuracy. The experimental results show that our flip-chip process is very reliable and promising for various optical and electrical applications and, thus, paves the way for fabrication of hybrid chips, multi-chip modules and chip-on-chip solutions, which are operated at cryogenic temperatures.

Heterogeneous Integration of Complementary Field-Effect Transistors for High-Performance Micro LED Displays.

This study investigates a micro light-emitting diode (µLED) pixel circuit using the heterogeneous integration of complementary field-effect transistors (CFETs). The CFETs are fabricated using a semiconductor layer composed of tellurium (Te) and indium-gallium-zinc oxide (IGZO) layers. Te and IGZO layers in the heterostructure IGZO/Te film exhibit hexagonal and amorphous phases, respectively, indicating that each layer maintains independent material characteristics. The fabricated IGZO/Te CFETs exhibit ambipolar behavior with a turn-on voltage of 2.0V and field-effect mobility of 0.74 and 1.42 cm2 V-1 s-1 for p-type and n-type channels, respectively. Inverters comprising IGZO/Te CFET and IGZO TFT exhibit inverting behavior. A µLED pixel circuit is designed using IGZO/Te CFETs based on pulse width modulation (PWM). The proposed circuit uses an inverter structure with IGZO/Te and IGZO to control the emission time, suppressing the wavelength shift of µLEDs depending on the µLED current levels. The operation of the proposed pixel circuit is investigated through simulation and measurement of the fabricated circuit. The fabricated µLED pixel circuit successfully exhibits PWM operation, controlling the emission time and luminance. Consequently, IGZO/Te CFETs show promise as devices for high-quality µLED displays.

Heterogeneous Integration of High Endurance Ferroelectric and Piezoelectric Epitaxial BaTiO3 Devices on Si

AbstractIntegrating epitaxial BaTiO3 (BTO) with Si is essential for leveraging its ferroelectric, piezoelectric, and nonlinear optical properties in microelectronics. Recently, heterogeneous integration approaches that involve growth of BTO on ideal substrates followed by transfer to a desired substrate show promise of achieving excellent device‐quality films. However, beyond simple demonstrations of the existence of ferroelectricity, robust devices with high endurance are not yet demonstrated on Si using the latter approach. Here, using a novel two‐step approach to synthesize epitaxial BTO using pulsed laser deposition on water‐soluble Sr3Al2O6 (on SrTiO3 substrates), successful integration of high‐quality BTO capacitors on Si is demonstrated, with remanent polarisation Pr = 7 µC cm−2, coercive field Ec = 150 kV cm−1, ferroelectric and electromechanical endurance of > 106 cycles. The study further addresses the challenge of cracking and disintegration of thicker films by first transferring a large area (5 mm x 5 mm) of the templated layer of BTO (≈30 nm thick) on the desired substrate, followed by the growth of high‐quality BTO on this substrate, as revealed by high‐resolution X‐ray diffraction (HRXRD) and high‐resolution scanning transmission electron microscopy (HRSTEM) measurements. These templated Si substrates offer a versatile platform for integrating any epitaxial complex oxides with diverse functionalities onto any inorganic substrate.

III-nitride semiconductor membrane electronics and optoelectronics for heterogeneous integration

III-nitride semiconductor membrane electronics and optoelectronics for heterogeneous integration

Transition of EDA Tools for Advanced Packages Supporting Heterogeneous Integration

Transition of EDA Tools for Advanced Packages Supporting Heterogeneous Integration

III-V-on-Si3N4 widely tunable narrow-linewidth laser based on micro-transfer printing

Leveraging its superior waveguide properties, silicon-nitride (Si3N4) photonics is emerging to expand the applications of photonic integrated circuits to optical systems where bulk optics and fibers today still dominate. In order to fully leverage its advantages, heterogeneous integration of III-V gain elements on Si3N4 is one of the most critical steps. In this paper, we demonstrate a III-V-on-Si3N4 widely tunable narrow-linewidth laser based on micro-transfer printing. Detailed design considerations of the tolerant III-V-to-Si3N4 vertical coupler, Si3N4-based micro-ring resonators (MRRs), and micro-heaters are discussed. By introducing the dispersion of Si3N4 waveguide in the design, the proposed Vernier MRRs enable an extended tuning range over multiple Vernier periods. The laser shows a wavelength tuning range of 54 nm in C and L bands with intrinsic linewidth less than 25 kHz. Within the tuning range, the side mode suppression ratio is larger than 40 dB and the output power in the Si3N4 waveguide reaches 6.3 mW. The integration process allows for the fabrication and quality control of both the Si3N4 circuits and III-V devices in its own foundry, which greatly enhances the integration yield and paves the way for large-scale integration.

Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al2O3 gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al2O3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm2/(V∙s), a subthreshold swing of 136 mV dec−1, and an on-/off-current ratio above 109. PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 109 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.

Active interface characteristics of heterogeneously integrated GaAsSb/Si photodiodes

There is increased interest in the heterogeneous integration of various compound semiconductors with Si for a variety of electronic and photonic applications. This paper focuses on integrating GaAsSb (with absorption in the C-band at 1550 nm) with silicon to fabricate photodiodes, leveraging epitaxial layer transfer (ELT) methods. Two ELT techniques—nanomembrane transfer printing and macro-transfer printing—are compared for transferring GaAsSb films from InP substrates to Si, forming PIN diodes. Characterization through atomic force microscopy and transmission electron microscopy exhibits a high-quality, defect-free interface. Current–voltage (IV) measurements and capacitance–voltage analysis validate the quality and functionality of the heterostructures. Photocurrent measurements at room temperature and 200 K demonstrate the device's photo-response at 1.55 μm, highlighting the presence of an active interface.

Bottom-Up Formation of III-Nitride Nanowires: Past, Present, and Future for Photonic Devices.

The realization of semiconductor heterostructures marks a significant advancement beyond silicon technology, driving progress in high-performance optoelectronics and photonics, including high-brightness light emitters, optical communication,and quantum technologies. In less than a decade since 1997, nanowires research has expanded into new application-driven areas,highlighting a significant shift toward more challenging and exploratory research avenues. It is therefore essential to reflecton the past motivations for nanowires development, and explorethe new opportunities it can enable. The advancement of heterogeneous integration using dissimilar substrates, materials, and nanowires-semiconductor/electrolyte operating platforms is ushering in new research frontiers, including the development of perovskite-embedded solar cells, photoelectrochemical (PEC) analog and digital photonic systems, such as PEC-basedphotodetectors and logic circuits, as well as quantum elements, such assingle-photon emitters and detectors. This review offersrejuvenating perspectives on the progress of these group-III nitride nanowires,aiming to highlight the continuity of research toward high impact, use-inspired researchdirections in photonics and optoelectronics.

Heterogeneous Integration of Wide Bandgap Semiconductors and 2D Materials: Processes, Applications, and Perspectives.

Wide-bandgap semiconductors (WBGs) are crucial building blocks of many modern electronic devices. However, there is significant room for improving the crystal quality, available choice of materials/heterostructures, scalability, and cost-effectiveness of WBGs. In this regard, utilizing layered 2D materials in conjunction with WBG is emerging as a promising solution. This review presents recent advancements in the integration of WBGs and 2D materials, including fabrication techniques, mechanisms, devices, and novel functionalities. The properties of various WBGs and 2D materials, their integration techniques including epitaxial and nonepitaxial growth methods as well as transfer techniques, along with their advantages and challenges, are discussed. Additionally, devices and applications based on the WBG/2D heterostructures are introduced. Distinctive advantages of merging 2D materials with WBGs are described in detail, along with perspectives on strategies to overcome current challenges and unlock the unexplored potential of WBG/2D heterostructures.

Precision-induced localized molten liquid metal stamps for damage-free transfer printing of ultrathin membranes and 3D objects

Transfer printing, a crucial technique for heterogeneous integration, has gained attention for enabling unconventional layouts and high-performance electronic systems. Elastomer stamps are typically used for transfer printing, where localized heating for elastomer stamp can effectively control the transfer process. A key challenge is the potential damage to ultrathin membranes from the contact force of elastic stamps, especially with fragile inorganic nanomembranes. Herein, we present a precision-induced localized molten technique that employs either laser-induced transient heating or hotplate-induced directional heating to precisely melt solid gallium (Ga). By leveraging the fluidity of localized molten Ga, which provides gentle contact force and exceptional conformal adaptability, this technique avoids damage to fragile thin films and improves operational reliability compared to fully liquefied Ga stamps. Furthermore, the phase transition of Ga provides a reversible adhesion with high adhesion switchability. Once solidified, the Ga stamp hardens and securely adheres to the micro/nano-membrane during the pick-up process. The solidified stamp also exhibits the capability to maneuver arbitrarily shaped objects by generating a substantial grip force through the interlocking effects. Such a robust, damage-free, simply operable protocol illustrates its promising capabilities in transfer printing diverse ultrathin membranes and objects on complex surfaces for developing high-performance unconventional electronics.

Beyond Flexible: Unveiling the Next Era of Flexible Electronic Systems.

Flexible electronics are integral in numerous domains such as wearables, healthcare, physiological monitoring, human-machine interface, and environmental sensing, owing to their inherent flexibility, stretchability, lightweight construction, and low profile. These systems seamlessly conform to curvilinear surfaces, including skin, organs, plants, robots, and marine species, facilitating optimal contact. This capability enables flexible electronic systems to enhance or even supplant the utilization of cumbersome instrumentation across a broad range of monitoring and actuation tasks. Consequently, significant progress has been realized in the development of flexible electronic systems. This study begins by examining the key components of standalone flexible electronic systems-sensors, front-end circuitry, data management, power management and actuators. The next section explores different integration strategies for flexible electronic systems as well as their recent advancements. Flexible hybrid electronics, which is currently the most widely used strategy, is first reviewed to assess their characteristics and applications. Subsequently, transformational electronics, which achieves compact and high-density system integration by leveraging heterogeneous integration of bare-die components, is highlighted as the next era of flexible electronic systems. Finally, the study concludes by suggesting future research directions and outlining critical considerations and challenges for developing and miniaturizing fully integrated standalone flexible electronic systems.

Wafer-scale integration of two-dimensional perovskite oxides towards motion recognition

Two-dimensional semiconductors have shown great potential for the development of advanced intelligent optoelectronic systems. Among them, two-dimensional perovskite oxides with compelling optoelectronic performance have been thriving in high-performance photodetection. However, harsh synthesis and defect chemistry severely limit their overall performance and further large-scale heterogeneous integration. Here, we report the wafer-scale integration of highly oriented nanosheets by introducing a charge-assisted oriented assembly film-formation process and confirm its universality and scalability. The shallow-trap dominance induced by structural optimization endows the device with a distinguished performance balance, including high photosensitivity close to that of single nanosheet units and fast response speed. An integrated ultra-flexible 256-pixel device demonstrates the versatility of material-to-substrate integration and conformal imaging functionality. Moreover, the device achieves efficient recognition of multidirectional motion trajectories with an accuracy of over 99.8%. Our work provides prescient insights into the large-area fabrication and utilization of 2D perovskite oxides in advanced optoelectronics.

Monolithic and heterogeneous three-dimensional integration of two-dimensional materials with high-density vias

Monolithic and heterogeneous three-dimensional integration of two-dimensional materials with high-density vias

Recent Developments in Low Temperature Wafer Level Metal Bonding for Heterogenous Integration

Abstract An overview of various low-temperature (<200°C) wafer bonding processes using metal interlayers is presented. Such processes are very attractive for novel applications in 3D heterogenous packaging as the allow for simultaneous formation of electrical interconnects, as well as hermetic encapsulation of various sensors and microelectromechanical systems-based devices. Metal wafer bonding is a generic category of processes consisting of various sub-categories, each one defined by the different principles governing the process. One can differentiate between eutectic wafer bonding (a eutectic alloy is formed as bonding layer during the process by liquid-solid interdiffusion), intermetallic wafer bonding (an intermetallic alloy is formed as bonding layer during the process by solid-liquid interdiffusion, a process known also as solid liquid intermetallic diffusion transient liquid phase, and metal thermo-compression wafer bonding. Different critical/gating parameters were investigated and their impact for generally reducing processing temperatures for the different metal bonding systems was studied.

Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)

Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)

Device-Performance-Driven Heterogeneous Multiparty Learning for Arbitrary Images.

Multiparty learning (MPL) is an emerging framework for privacy-preserving collaborative learning. It enables individual devices to build a knowledge-shared model and remaining sensitive data locally. However, with the continuous increase of users, the heterogeneity gap between data and equipment becomes wider, which leads to the problem of model heterogeneous. In this article, we concentrate on two practical issues: data heterogeneous problem and model heterogeneous problem, and propose a novel personal MPL method named device-performance-driven heterogeneous MPL (HMPL). First, facing the data heterogeneous problem, we focus on the problem of various devices holding arbitrary data sizes. We introduce a heterogeneous feature-map integration method to adaptively unify the various feature maps. Meanwhile, to handle the model heterogeneous problem, as it is essential to customize models for adapting to the various computing performances, we propose a layer-wise model generation and aggregation strategy. The method can generate customized models based on the device's performance. In the aggregation process, the shared model parameters are updated through the rules that the network layers with the same semantics are aggregated with each other. Extensive experiments are conducted on four popular datasets, and the result demonstrates that our proposed framework outperforms the state of the art (SOTA).

Flexible electronic-photonic 3D integration from ultrathin polymer chiplets

Integrating flexible electronics and photonics can create revolutionary technologies, but combining these components on a single polymer device has been difficult, particularly for high-volume manufacturing. Here, we present a robust chiplet-level heterogeneous integration of polymer-based circuits (CHIP), where ultrathin polymer electronic and optoelectronic chiplets are vertically bonded at room temperature and shaped into application-specific forms with monolithic Input/Output (I/O). This process was used to develop a flexible 3D integrated optrode with high-density microelectrodes for electrical recording, micro light-emitting diodes (μLEDs) for optogenetic stimulation, temperature sensors for bio-safe operations, and shielding designs to prevent optoelectronic artifacts. CHIP enables simple, high-yield, and scalable 3D integration, double-sided area utilization, and miniaturization of connection I/O. Systematic characterization demonstrated the scheme’s success and also identified frequency-dependent origins of optoelectronic artifacts. We envision CHIP being applied to numerous polymer-based devices for a wide range of applications.

Heterogeneous Integration of 42°YX LiNbO₃/SiO₂/Quartz for Wideband and Spurious-Free SAW Resonators

Heterogeneous Integration of 42°YX LiNbO₃/SiO₂/Quartz for Wideband and Spurious-Free SAW Resonators

Thresholding Computing with Heterogeneous Integration of Memristive Kernel with Metal-Oxide-Semiconductor Capacitor for Temporal Data Analysis.

Precise event detection within time-series data is increasingly critical, particularly in noisy environments. Reservoir computing, a robust computing method widely utilized with memristive devices, is efficient in processing temporal signals. However, it typically lacks intrinsic thresholding mechanisms essential for precise event detection. This study introduces a new approach by integrating two Pt/HfO2/TiN (PHT) memristors and one Ni/HfO2/n-Si (NHS)metal-oxide-semiconductor capacitor (2M1MOS) to implement a tunable thresholding function. The current-voltage nonlinearity of memristors combined with the capacitance-voltage nonlinearity of the capacitor forms the basis of the 2M1MOS kernel system. The proposed kernel hardware effectively records feature-specified information of the input signal onto the memristors through capacitive thresholding. In electrocardiogram analysis, the memristive response exhibited a more than ten-fold difference between arrhythmia and normal beats. In isolated spoken digit classification, the kernel achieved an error rate of only 0.7% by tuning thresholds for various time-specific conditions. The kernel is also applied to biometric authentication by extracting personal features using various threshold times, presenting more complex and multifaceted uses of heartbeats and voice data as bio-indicators. These demonstrations highlight the potential of thresholding computing in a memristive framework with heterogeneous integration.