The demand for the high-density integrated memories is growing along with the scaling of the transistor technology nodes. To fabricate the reliable devices in advanced technologies, optimization of several process steps is necessary [1]. The capacitor, which is commonly a MIM (Metal-Insulator-Metal) module finds its application as a basic storage device in memories, filters, voltage limiters etc. The MIM module is also considered as an integral part of memory technologies such as DRAM, FeRAM, and RRAM. The MIM modules should demonstrate reliable operation through better performance and efficiency. And, it is realized through the parameters related to MIM module such as, low leakage current, less variability with respect to capacitance, high quality factor Q, lower defect density, low parasitic capacitance and many others [2]. Reactive-ion-etching plays a very important role in BEOL integration of MIM devices. The MIM module is created by dry etching through the MIM stack. Related to RRAM (Resistive Random Access Memory) applications the MIM stack consists of an additional buffer layer such as Ti or Hf [3]. These layers are easily oxidizable and the etching step could oxidize them from the sidewalls. Also, the residuals of the metal if remain on the sidewall could lead to leaky devices. Hence, an etch process which is not well optimized could damage the devices and in turn pose a threat to their functionality and reliability [4]. An improved MIM stack etch process is beneficial to reduce the above-mentioned damages. Several techniques were used in the past to cover the MIM devices with dielectric materials like SiO2 and SiN, which protects the devices from further process steps involved in the fabrication procedure [5]. In this work we demonstrate the effect of the improved etch process with a combination of SiNO spacers and encapsulation techniques for TiN/Ti/HfO2/TiN stacks. This stack is most popularly used in RRAM and, in this work, it is integrated into the BEOL of the 250 nm CMOS technology at IHP. To test the performance of the devices, the MIM stack was fabricated in three different approaches. In the first approach, photoresist is used as a mask to etch the MIM stack, the second one uses TiN hard mask and the third one uses TiN hard mask etch in addition to creation of SiNO spacers after the TiN/Ti etch. The encapsulation of MIM modules with SiNO is implemented in all the three approaches mentioned above. Special device structures with the TiN/Ti/HfO2/TiN stack are fabricated to test the variability of the MIM parameters on the entire wafer. Additionally, the switching operation was tested by means of DC voltage sweeps on the MIM RRAM devices which includes, forming, reset and set steps followed by 50 cycles of reset and set processes. The devices associated with the improved fabrication process steps exhibited less variability in terms of leakage current, capacitance and Q-factor values along the entire wafer. This reduction in the variability of the parameters corresponding to the MIM devices could be used for emerging applications. References G.S. Kar, A.Fantini, Y.Y. Chen, V. Paraschiv, B. Govorenau, H. Hody, N. Jossart, H.Tielens, S. Brus, O. Richard, T. Vandeweyer, D.J. Wouters, L. Altimime, M. Jurczak, i n Symposium on VLSI Technology (VLSIT), 2012 IEEE, pp. 157-158E. Pérez, A. Grossi, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and Ch. Wenger, in MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), 2018 IEEE, pp. 1-3E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, and Ch. Wenger, Solid-State Electronics, (2019) V. B. Naik, J. H. Lim, K. Yamane, D. Zeng, H. Yang, N. Thiyagarajah, J. Kwon, N. L. Chung, R. Chao, T. Ling, K. Lee, in International Reliability Physics Symposium (IRPS), 2019 IEEE, pp. 2C-2Y.S. Chen, H.Y. Lee, P.S. Chen, P.Y. Gu, W.H. Liu, W.S. Chen, Y.Y. Hsu, C.H. Tsai, F. Chen, M.J. Tsai, and C. Lien, Electron Device Letters, Vol. 32, Issue: 3, pp 390-392 (2011)
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Open Access
Jul 1, 2022
Ilona Rolfes 