MTCMOS Circuit Research Articles

Performance Analysis of High Speed Domino CMOS Logic Circuits

the demand of low power high performance arithmetic circuits multiplies, during this paper, we aim to introduce a style of latest MT-CMOS domino logic and FTL dynamic logic technique to style adder circuit. The MT-MOS transistors cut back the facility dissipation by minimizing sub threshold run current in the introduced domino logic circuits. The MT-NMOS semiconductor connected in discharging path of output electrical converter may be applied for pipeline structure to scale back the facility consumptions and increase fan-out. Dynamic logic vogue CMOS circuit is employed to enhance the speed and cut back the world of style by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly perform a final evaluation as soon as the inputs arrive. This dynamic logic formation is like minded for an arithmetic circuit wherever the important path s created of an outsized cascade of inverting gates is created. The mixture of MT-CMOS and dynamic logic circuit provides high fan-out, high change frequencies with each lower delay and dynamic power consumption. The simulation results of those projected low power high performance circuits provide 75% power reduction, three times redoubled high speed operation and active space reduction, whereas revealing lower sensitivity to power provide, temperature, electrical phenomenon load and method variations than the dynamic domino CMOS technologies.

Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSI's) for battery-driven portable equipment. The balloon circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices.