MQ Coder Research Articles

VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder

The MQ arithmetic coding, which is an adaptive arithmetic coding developing from Q coding, has become a major throughput bottleneck of JPEG2000 compression due to its inherent serial operations. To overcome the bottleneck, this brief proposes a high-performance hardware architecture of the multicontext MQ coder. The proposed architecture is capable of concurrent coding for two adjacent more probable symbols (MPSs). Performance analysis results show that the proposed coder consumes 1.61 CXD pairs per cycle and achieves a throughput of 506.93 MSymbols/s under 0.5 bpp bit rate. The proposed architecture not only achieves high throughput, but also maintains both low hardware utilization and low power consumption. Compared with the state-of-the-art two-context coder, the figure of merit (FoM) is increased by 38%. Compared with the single-context coder, the power-delay product (PDP) is reduced by 49%.

Enhanced Binary MQ Arithmetic Coder with Look-Up Table

Binary MQ arithmetic coding is widely used as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as a unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity that happens in the MQ coder, the output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of look-up table (LUT) for (A × Qe) using quantization skill to improve the coding efficiency. Multi-level quantization using 2-level, 4-level and 8-level look-up tables is proposed in this paper. Experimental results applying to binary documents show about 3% improvement for basic context-free binary arithmetic coding. In the case of JBIG2 bi-level image compression standard, compression efficiency improved about 0.9%. In addition, in the case of lossless JPEG2000 compression, compressed byte decreases 1.5% using 8-level LUT. For the lossy JPEG2000 coding, this figure is a little lower, about 0.3% improvement of PSNR at the same rate.

2진 MQ 산술부호기의 성능 개선

2진(binary) MQ 산술부호화는 최근 들어 멀티미디어 압축 표준시스템에 기본 엔트로피 방식으로 사용되고 있다. MQ 산술부호기는 JBIG2와 JPEG2000에 적용되면서 압축성능을 인정받기 시작했다. 최근에 차세대 동영상 부호화 표준인 HEVC (high efficiency video coding)에는 산술부호화가 단일 엔트로피부호화로 채택되면서 그 중요성이 커지고 있다. 기존의 2진 MQ 산술부호기는 RANGE(구간)을 분할하는 과정에서 곱셈을 없애면서 근사화 방법을 사용하고 있다. 이 경우 MPS/LPS의 구간이 뒤바뀌는 경우가 발생하며 출력비트가 늘어날 수 있다. 본 논문에서는 이러한 문제점을 완화하기 위하여 근사식을 사용하는 대신에 룩업테이블 형태로 AQe의 값을 양자화하여 계산에 적용하는 방법을 제안하고자 한다. 제안한 방법의 압축 성능을 실험을 통해 확인한 결과, 2진영상 압축표준 방식인 JBIG2의 경우 약 4%의 압축율의 개선을 보였다. 정지영상 압축표준인 JPEG2000의 경우 약 1%정도의 개선을 가져왔다. 룩업테이블을 사용하기 때문에 계산량이 기존방법에 비해 늘지 않는다. Binary MQ arithmetic coding is widely used recently as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as an unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity happened in MQ coder, output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of a lookup table for AQe using quantization skill in order to reduce the deficiency. Experimental results show that about 4% improvement of compression in case of JBIG2 for bi-level image compression standard. And also, about 1% improvement of compression ratio is obtained in case of lossless JPEG2000 coding. For the lossy JPEG2000 coding, about 1% improvement of PSNR at the same compression ratio. Additionally, computational complexity is not increasing.

Context-Adaptive Binary Arithmetic Coding With Fixed-Length Codewords

Context-adaptive binary arithmetic coding is a widespread technique in the field of image and video coding. Most state-of-the-art arithmetic coders produce a (long) codeword of a priori unknown length. Its generation requires a renormalization procedure to permit progressive processing. This paper introduces two arithmetic coders that produce multiple codewords of fixed length. Contrary to the traditional approach, the generation of fixed-length codewords does not require renormalization since the whole interval arithmetic is stored in the coder’s internal registers. The proposed coders employ a new context-adaptive mechanism based on variable-size sliding window that estimates with high precision the probability of the symbols coded. Their integration in coding systems is straightforward as demonstrated within the framework of JPEG2000. Experimental tests indicate that the proposed coders are computationally simpler than the MQ coder of JPEG2000 and the M coder of HEVC while achieving superior coding efficiency.

Secure MQ coder: An efficient way to protect JPEG 2000 images in wireless multimedia sensor networks

This paper presents a secure MQ coder (SMQ) for efficient selective encryption of JPEG 2000 images. Being different from existing schemes where encryption overhead is proportional to the size of plain image, SMQ only selectively encrypts tiny and constant volume of data in JPEG 2000 coding regardless of image size. It is extremely fast and suitable for protecting JPEG 2000 images in wireless multimedia sensor networks (WMSNs). Theoretical analysis and experimental results show that SMQ can achieve a balance between security and efficiency, while keeping comparable compression performance and energy consumption with standard JPEG 2000 coding.

Area Efficient, High Speed EBCOT Architecture for Digital Cinema

Embedded block coding with optimised truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. To meet this challenge, the relationship between contents of a code block (CB) and context generation is studied. Our study reveals that it is difficult to predict number of contexts generated in a bit plane. Even the nature of number of contexts produced varies from CB to CB. In such a situation, it is difficult to ensure the frame rate requirement of DC. To avoid this uncertainty, a pass parallel, concurrent sample coding EBCOT architecture is proposed in this paper. It is capable of encoding one bit plane in 288 clock cycles under any circumstances. This design is prototyped on XC4VLX80-12 FPGA with multiple clock domains. After synthesizing, the bit plane coder (BPC) and MQ coder operate at 450 MHz and 123 MHz, respectively. In order to maintain synchronism among different clock domains, the BPC and MQ coder units are operated at 432 MHz and 108 MHz, respectively. This entails that the proposed design is capable of processing size 57 DC frames in a second.

Adaptive Binary Arithmetic Coder‐Based Image Feature and Segmentation in the Compressed Domain

Image compression is necessary in various applications, especially for efficient transmission over a band‐limited channel. It is thus desirable to be able to segment an image in the compressed domain directly such that the burden of decompressing computation can be avoided. Motivated by the adaptive binary arithmetic coder (MQ coder) of JPEG2000, we propose an efficient scheme to segment the feature vectors that are extracted from the code stream of an image. We modify the Compression‐based Texture Merging (CTM) algorithm to alleviate the influence of overmerging problem by making use of the rate distortion information. Experimental results show that the MQ coder‐based image segmentation is preferable in terms of the boundary displacement error (BDE) measure. It has the advantage of saving computational cost as the segmentation results even at low rates of bits per pixel (bpp) are satisfactory.

Texture segmentation in the joint photographic expert group 2000 domain

Image segmentation is an important task in many image processing systems. For efficient transmission over a band-limited channel, original images are often compressed before being stored in databases. In order to avoid the burden of decompressing an image, it is desirable to extract features directly from a code stream. This approach saves computational time significantly. The look up table used for the MQ coder defined in joint photographic expert group 2000 (JPEG2000) called the MQ table provides probability models for bit-plane coding of wavelet coefficients, the wavelet histogram information can be obtained directly from a JPEG2000 code stream. Thus, the MQ feature based on the MQ table is proposed to segment an image in the JPEG2000 domain directly. Experimental results of clustering these features by using the simple K-means algorithm show the potential of MQ feature.

VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000

The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. The MQ coder used in this algorithm restricts throughput of the EBCOT because there is very high correlation among all procedures to be performed in it. To overcome this obstacle, a high throughput MQ coder architecture is presented in this paper. To accomplish this, we have studied the number of rotations performed and the rate of byte emission in an image. This study reveals that in an image, on an average 75.03% and 22.72% of time one and two shifts occur, respectively. Similarly, about 5.5% of time two bytes are emitted concurrently. Based on these facts, a new MQ coder architecture is proposed which is capable of consuming one symbol per clock cycle. The throughput of this coder is improved by operating the renormalization and byte out stages concurrently. To reduce the hardware cost, synchronous shifters are used instead of hard shifters. The proposed architecture is implemented on Stratix FPGA and is capable of operating at 145.9 MHz. Memory requirement of the proposed architecture is reduced by a minimum of 66% compared to those of the other existing architectures. Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost.

Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000

The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc. This paper presents a detailed performance analysis for EBCOT Tier-1 and its bit plane parallel architecture design. By analyzing the bit plane parallel context modeling, we conclude that the difference between the output rate of context modeling module and that of arithmetic coding module degrades the performance of whole EBCOT parallel encoding. We propose two improved methods, referred to as data-pairs ordering (DPO) and flexible MQ (FMQ) coder. It solves the configuration problem between the parallel context modeling module and the sequent arithmetic coding module, takes full advantage of the bit plane parallel encoding technique, and improves the coding speed and efficiency of the EBCOT encoder significantly. The design of parallel EBCOT encoder is tested on the field-programmable gate array (FPGA) platform of Altera Company. The simulation results show that it can on average encode 54 million samples at 55-MHz working frequency. It is equivalent to encoding a 90006000 image per second or encoding 720 p (1280times720, 4:2:2) HDTV picture sequence nearly 30 frames per second. Compared with the conventional bit plane parallel architecture design, the proposed one can reduce execution time by 24%.

Novel architecture for the JPEG2000 block coder

JPEG2000 is the newest international standard to be produced by the Joint Photographic Experts Group (JPEG) and it has recently been published as an International Standards Organization/IEC standard and as an ITU-T recommendation. It complements most of the currently used standards including the original JPEG, usually with superior compression for the same image quality, or alternatively with superior image quality for the same bit rate. The algorithm uses the wavelet transform followed by an embedded block coder incorporating the MQ arithmetic coder. In this article we give a novel hardware architecture for the block coder and MQ coder as used in the JPEG2000 standard. Together with appropriate software, this design enables a high performance system-on-chip solution for JPEG2000 image compression. We have included sufficient introductory material to interest readers unfamiliar with either JPEG2000 or hardware design.