MPEG-4 Simple Profile Research Articles

Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow

The tradeoff between analyzability and expressiveness is a key factor when choosing a suitable dataflow model of computation (MoC) for designing, modeling, and simulating applications considering a formal base. A large number of techniques and analysis tools exist for static dataflow models, such as synchronous dataflow. However, they cannot express the dynamic behavior required for more dynamic applications in signal streaming or to model runtime reconfigurable systems. On the other hand, dynamic dataflow models like Kahn process networks sacrifice analyzability for expressiveness. Scenario-aware dataflow (SADF) is an excellent tradeoff providing sufficient expressiveness for dynamic systems, while still giving access to powerful analysis methods. In spite of an increasing interest in SADF methods, there is a lack of formally-defined functional models for describing and simulating SADF systems. This article overcomes the current situation by introducing a functional model for the SADF MoC, as well as a set of abstract operations for simulating it. We present the first modeling and simulation tool for SADF so far, implemented as an open source library in the functional framework ForSyDe. We demonstrate the capabilities of the functional model through a comprehensive tutorial-style example of a RISC processor described as an SADF application, and a traditional streaming application where we model an MPEG-4 simple profile decoder. We also present a couple of alternative approaches for functionally modeling SADF on different languages and paradigms. One of such approaches is used in a performance comparison with our functional model using the MPEG-4 simple profile decoder as a test case. As a result, our proposed model presented a good tradeoff between execution time and implementation succinctness. Finally, we discuss the potential of our formal model as a frontend for formal system design flows regarding dynamic applications.

Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs

Considering the evolution towards highly variable data flow applications based on an increasing impact of dynamic actors, we must target at runtime the best matching between dataflow graphs and heterogeneous multiprocessor platforms. Thus the mapping must be dynamically adapted depending on data and on communication loads between the computation cores. This is typically the case for mobile devices that run multimedia applications. The problem of mapping a dataflow application, e.g. a network of computational actors, on a multiprocessor platform can be modeled as a problem of partitioning where the cells are the dataflow actors and the partitions are the processors. While the benefit of executing a computational part by one processor rather than another one is usually well shown, the migration overhead is also usually not considered. This paper presents a dynamic mapping algorithm that is performed at runtime, based on a single-move possibility that jointly considers the cost and benefit of possible migrations. The method is first applied on a set of randomly generated benchmarks with different features and different scenarios. Then it is applied to a MPEG4 simple profile video decoder with different input sequences. The results systematically show that the runtime mapping significantly improves the initial mapping. It is fast enough to be executed at runtime in order to track the best mapping according to data variations. The other observation is that not considering the migration cost of the new mapping could lead to worst performance than the original one.

All Phase Biorthogonal Transform and Its Application in MPEG-4 Video Compression

In this paper, we propose an efficient algorithm for encoding of MPEG-4 simple profile. In the proposed algorithm, I frame encoding adopts all phase biorthogonal transform (APBT); for P frames, each frame puts the reconstructed frame of previous coded one as the reference frame to perform motion estimation (ME) and motion compensation (MC), and then the encoding of residual frame uses discrete cosine transform (DCT). While the proposed algorithm applying on MPEG-4, the objective effect and visual quality of reconstructed video sequence are approximate to the one based on DCT at the same bit rates. But the advantage is that the APBT transform coefficients can be quantized uniformly. Therefore the computing time is shorted and hardware implementation becomes easier. The proposed algorithm uses low computational complexity to make it applicable to encoding of MPEG-4 simple profile.

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems.This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism.The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.

Dynamic task partition for video decoding on heterogeneous dual-core platforms

This article presents the design of a video decoder using dynamic task partition approach on a heterogeneous dual-core embedded platform. For such systems, static task partition between the two cores at design time is a typical approach for application development. In this article, we propose a runtime dynamic task partition model and implement an MPEG-4 Simple Profile video decoder using this approach on a TI OMAP 5912 platform. Comparing with a traditional mobile video decoder optimized for the same DSP core, the performance gain from dynamic task partition is 38.4% on average. More importantly, the gain is achieved with the design constraint that the implementation effort for the dynamic task partition decoder is about the same as the effort using design-time task partition model. Unlike common belief that the inter-processor communication overhead would be too high to justify intense cooperation between two heterogeneous cores, this paper shows that it is indeed beneficial to adopt dynamic task partition model on commercially available heterogeneous multi-core platforms.

Zero coefficient-aware IDCT algorithm for fast video decoding

Ever since many well-known image and video coding standards such as JPEG, MPEG, and H.26x started using DCT as a core process in data compression, the design of the fast inverse discrete cosine transform (IDCT) has been an intensive research topic. Most research has focused on a reduction of the number of operations using the butterfly structure. However, the majority of DCT coefficients is zero after quantization and is therefore redundant for IDCT computation. Therefore, we exploited this DCT coefficients redundancy to propose a zero coefficient-aware IDCT algorithm for fast decoding. The proposed method significantly reduces the number of IDCT operations by adaptively including non-zero coefficients in the calculation and employing a table look-up to eliminate multiplication operations in the IDCT process. The proposed zero coefficient-ware algorithm outperformed other existing fast IDCT algorithms in terms of operational complexity. Moreover, the running time was faster than butterfly based IDCT algorithms implemented in MPEG-4 simple profile decoder by a speedup factor of 1.32 times for the SIF/CIF sequences and up to 2.18 times for the HD sequences.

Modeling DV/DVCPRO Standards on Reconfigurable Video Coding Framework

After more than 20 years, several video coding standards and technologies have been delivered. Less consideration is taken on their commonalities and interoperations. Specification and reference code of case by case is time consuming. The MPEG reconfigurable video coding (RVC) framework is a new standard under development by MPEG. It aims to provide a unified high‐level specification of current MPEG video coding technologies. In this framework, the decoder is built as a configuration of video coding tools taken from MPEG toolbox library. Up to now, MPEG‐4 simple profile and China audio video coding standard (AVS) decoders have been successfully modeled with RVC framework. In this paper, we examine another video standard, that is, DV/DVCPRO, and model it with RVC‐CAL. The flexibility and ease of RVC‐CAL is demonstrated as well as the validation of RVC modeling.

Fast entropy decoding method for high resolution personal video recorder

In this paper, we propose a fast entropy decoding method that is well suited for personal video recorder (PVR) applications for high resolution video (HRV). In PVR applications supporting HRV, it is essential to implement a fast encoder and decoder due to the large amount of video data. The proposed bit-precision based entropy method (BPEM) provides a way to design a very simple entropy decoding process, which can substantially reduce the overall computational complexity of the decoder. For the purpose of contents protection, it is common to have a proprietary codec in PVR. In such a case, additional transcoding for storing transmitted data is required. However, this may involve a complex process that requires encoding and decoding. The proposed method is only applied to the entropy coding method of the existing standard codecs for transcoding thereby reducing the transcoding complexity down to bitstream-level symbol mapping. We implemented BPEM on an MPEG-4 simple profile (SP) codec. The experimental results showed that BPEM produced about 30 percent lower decoder complexity and 50 to 80 percent lower syntax parsing time while maintaining similar coding efficiency compared to the conventional MPEG-4 SP codec.

Synthesizing Hardware from Dataflow Programs

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

Software Code Generation for the RVC-CAL Language

The MPEG Reconfigurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current and future MPEG video coding technologies using dataflow models. In this framework, a decoder is built as a configuration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. The generated code is validated against the original CAL description simulated using the Open Dataflow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Profile decoder with different granularities are shown and discussed.

Efficient MPEG-4 to H.264/AVC Transcoding with Spatial Downscaling

Efficient downscaling in a transcoder is important when the output should be converted to a lower resolution video. In this letter, we suggest an efficient algorithm for transcoding from MPEG-4 SP (with simple profile) to H.264/AVC with spatial downscaling. First, target image blocks are classified into monotonous, complex, and very complex regions for fast mode decision. Second, adaptive search ranges are applied to these image classes for fast motion estimation in an H.264/AVC encoder with predicted motion vectors. Simulation results show that our transcoder considerably reduces transcoding time while video quality is kept almost optimal.

Versatile PC/FPGA-Based Verification/Fast Prototyping Platform With Multimedia Applications

For most integrated circuit (IC) design houses, building a dedicated field-programmable gate array (FPGA) verification board before the chip is tapped out is usually a requirement. The time and money spent on such boards are usually high. A versatile verification/fast prototyping platform consisting of an FPGA board and the associated System Software is presented. The FPGA board is connected to the host computer through a peripheral component interconnect interface. The System Software running on a Microsoft Windows environment is developed so that all the real-time data that were generated during the verification process can be downloaded and displayed on the host computer. Hence, the system acts like a logic analyzer with very large storage memory. Furthermore, the software provides interfaces for personal computer peripherals, such as a Universal Serial Bus camera, a computer monitor, and a soundcard, if the test data for multimedia applications are necessary. The results can be also demonstrated in real time through these devices. Because multimedia data are usually complicated, and the size is huge, the design and thorough verification are usually difficult and take lots of time. The proposed system is both versatile and convenient to use, and verification of designs becomes much easier. An MPEG-4 Simple Profile Video Encoder and a 3-D surround sound processor were realized with the proposed system. Both cases can run in real time. In this paper, the highly complicated H.264/Advanced Video Coding I-Frame encoder is also used to demonstrate the proposed system.

SPRINT: A Tool to Generate Concurrent Transaction-Level Models from Sequential Code

A high-level concurrent model such as a SystemC transaction-level model can provide early feedback during the exploration of implementation alternatives for state-of-the-art signal processing applications like video codecs on a multiprocessor platform. However, the creation of such a model starting from sequential code is a time-consuming and error-prone task. It is typically done only once, if at all, for a given design. This lack of exploration of the design space often leads to a suboptimal implementation. To support our systematic C-based design flow, we have developed a tool to generate a concurrent SystemC transaction-level model for user-selected task boundaries. Using this tool, different parallelization alternatives have been evaluated during the design of an MPEG-4 simple profile encoder and an embedded zero-tree coder. Generation plus evaluation of an alternative was possible in less than six minutes. This is fast enough to allow extensive exploration of the design space.

A Systematic Approach to Design Low-Power Video Codec Cores

The higher resolutions and new functionality of video applications increase their throughput and processing requirements. In contrast, the energy and heat limitations of mobile devices demand low-power video cores. We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation. First, memory optimizations are combined with algorithmic tuning. Then, a partitioning exploration introduces parallelism using a cyclo-static dataflow model that also expresses implementation-specific aspects of communication channels. Towards hardware, these channels are implemented as a restricted set of communication primitives. They enable an automated RTL development strategy for rigorous functional verification. The FPGA/ASIC design of an MPEG-4 Simple Profile video codec demonstrates the methodology. The video pipeline exploits the inherent functional parallelism of the codec and contains a tailored memory hierarchy with burst accesses to external memory. 4CIF encoding at 30 fps, consumes 71 mW in a 180 nm, 1.62 V UMC technology.

Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems

3-D video will be the most prominent video technology in the next generation. Among the 3-D video technologies, stereo video systems are considered to be realized first in the near future. Stereo video systems require double bandwidth and more than twice the computational complexity relative to mono-video systems. Thus, an efficient coding scheme is necessary for transmitting stereo video. In this paper, a new structure of prediction core in stereo video coding systems is proposed from the algorithm level to the hardware architecture level. The joint prediction algorithm (JPA), which combines three prediction schemes, is proposed for high coding efficiency and low computational complexity. It makes the system outperform MPEG-4 temporal scalability and simple profile by 2-3 dB in rate-distortion performance. Besides, JPA also utilizes the characteristics of stereo video and successfully reduces about 80% computational complexity. Then, a new hardware architecture of the prediction core based on JPA and a modified hierarchical search block-matching algorithm is proposed. With a special data flow, no bubble cycles exist during the block-matching process. The proposed architecture also adopts the near-overlapped candidates reuse scheme to save the heavy burden of data access. Besides, both on-chip memory requirement and off-chip memory bandwidth can be reduced by the proposed new scheduling. Compared with the hardware requirement for the implementation of full search block-matching algorithm, only 11.5% on-chip SRAM and 3.3% processing elements are needed with a tiny PSNR drop, making it area-efficient while maintaining high stereo video quality and processing capability

A fast block-matching algorithm based on variable shape search

Block-matching motion estimation plays an important role in video coding. The simple and efficient fast block-matching algorithm using Variable Shape Search (VSS) proposed in this paper is based on diamond search and hexagon search. The initial big diamond search is designed to fit the directional centre-biased characteristics of the real-world video sequence, and the directional hexagon search is designed to identify a small region where the best motion vector is expected to locate. Finally, the small diamond search is used to select the best motion vector in the located small region. Experimental results showed that the proposed VSS algorithm can significantly reduce the computational complexity, and provide competitive computational speedup with similar distortion performance as compared with the popular Diamond-based Search (DS) algorithm in the MPEG-4 Simple Profile.

Perceptual quality and objective quality measurements of compressed videos

This paper firstly presents a study of video quality for H.264 compressed videos compared to MPEG-4 (simple profile) from a perceptual point of view. Traditionally, peak signal-to-noise ratio (PSNR) has been used to represent the quality of a compressed video sequence. However, PSNR has been found to correlate poorly with subjective quality ratings, particularly at much lower bitrates and low frame rates. Thus, an alternative that has been commonly used is to perform subjective test where a large number of human subjects are used to gauge the quality of a video. However, this process is not only time-consuming but also tedious and expensive to perform. Hence, this paper further proposes an objective video quality measurement method to automatically measure the perceptual quality of a stream of video images. The proposed method has been tested on multimedia videos, consisting of CIF and QCIF video sequences compressed at various bitrates (24–384 kbps) and frame rates (7.5–30 fps) using the H.264 and MPEG-4 video codecs and it is shown to give significantly better correlations to the human perception than PSNR and the video structural similarity method.

Rate control for MPEG-2 SNR scalability and stream morphing using codeword estimation and overhead modelling

Many encoder architectures, notably for scalable systems such as MPEG-2 SNR scalability and stream morphing, require DCT-domain techniques for the estimation of the rate-distortion characteristics of a video frame for use in the rate control process. This paper develops a CBR rate control framework that can be used for single-layer MPEG-4 Simple Profile as well as two MPEG-4-based scalable systems, one following the structure described in MPEG-2 and also stream morphing. The framework supports perceptual quantization and also low bit rate operation by modelling macroblock overhead as well as the bits required to code non-zero DCT coefficients. Experimental results demonstrate the performance of stream morphing, in both objective and subjective measures, is in almost all cases superior to the MPEG-2 SNR scalability and MPEG-4 Fine Granularity Scalability.

Efflcient implementation of MPEG-4 video encoder on RISC core

MPEG-4 simple profile video is being used as the video compression standard in mobile video communications. MPEG-4 video requires more computational power because of its high complexity. Currently, RISC cores are widely used in mobile applications because of their low power consumption. Design of fully standard-complaint MPEG-4 video encoder with real time performance on a RISC processor for embedded applications entails optimizations at all levels to the maximum extent possible. This paper describes in detail about the implementation of MPEG-4 simple profile video encoder on efficient RISC processor core requiring 50 Mega Cycles to encode QCIF resolution video at 15 frames per second with minimum processing power and memory requirements.

Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors

This paper describes an efficient motion estimation algorithm, the predictive line search (PLS), for real-time implementations of MPEG-4 encoder on multimedia processors. The motion-vector predictor is used as the starting point in the search process because the correlation between neighboring motion vectors is strong. The line search pattern is used in the proposed algorithm to reduce the memory access as well as to exploit the special multimedia processor instructions for sum of absolute difference calculations. Experimental results show that the performance of the PLS is very close to that of the full-search (FS) algorithm. Compared with the well-known diamond search and one-dimensional FS, the PLS shows better performance and robustness, especially for high motion sequences. A prototype MPEG-4 encoding system is implemented on a 216-MHz multimedia processor with very long instruction word architecture to verify the effectiveness of the PLS. Real-time encoding of MPEG-4 Simple Profile Level 3 (CIF, 30 fps) can be achieved with only 57% of the processor load.