Movable Terminals Research Articles

Status of a 200-Meter DC Superconducting Power Transmission Cable After Cooling Cycles

We constructed a facility of a 200-m HTS power transmission test cable (CASER-II) in 2010. Generally, an HTS cable contracts about 0.3% when it is cooled from room temperature to liquid nitrogen (LN2) temperature. The contraction of the 200-m HTS cable corresponds to 0.6 m. In order to realize the HTS power transmission system, it is an essential issue to absorb the mechanical stress of the HTS cable during the cycles of cooling-down and heating-up. The CASER-II uses smooth pipes as the cryogenic pipe for the cable line to reduce the pressure drop of the liquid nitrogen flow, whereas the other HTS cables use corrugated pipes to absorb the mechanical stress. The CASER-II employed (1) the movable terminals at the cable end, and (2) the extendable bellows inserted in the cryogenic pipe, to absorb the contraction of 0.6 m in cooling cycles. Even at the 4th cooling-down test, no damage was observed in the CASER-II. Use of the smooth cryogenic pipe enabled low pressure drop with low LN2 flow rate, and negative pressure drop appeared at less than 5 L/sec of the LN2 flow rate. This negative pressure drop was caused by the LN2 flow assisted by siphon effect due to the difference of LN2 density along the cryogenic pipe line with elevation of 2.6 m.

Minimizing channel density with movable terminals

We give algorithms to minimize density for VLSI channel-routing problems with terminals that are movable subject to certain constraints. The main cases considered are channels with linear-order constraints, channels with linear-order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case we improve previous results for running time and space by a factor ofL/lgn andL, respectively, whereL is the channel length andn is the number of terminals.

Correction to "Boundary single-layer routing with movable terminals"

In boundary single-layer routing with slidable or permutable terminals (BSLR-S or BSLR-P), the assumption that each net may have more than one terminal in a range or cluster should be removed. An example that shows Pick-Closest might report "unsolvable" for a solvable instance is considered. It is clear that the instance is solvable if (and only if) the two terminals of net N/sub 1/ are assigned to vertices c and d. However, Pick-Closest will assign the two terminals of net N/sub 1/ to vertices /spl lcub/b,c/spl rcub/ or /spl lcub/d,e/spl rcub/, then report "unsolvable" due to the failure in routing net N/sub 2/. Thus, Pick-Closest only works in instances when each net has at most one terminal in a range. Since BSLR-P also includes slidable terminals, we employ Pick-Closest to solve BSLR-P when TR-permutation is determined by Greedy-Assignment. Thus in BSLR-P, each net can have at most one terminal in a cluster as well. The time complexity of the problem of boundary single-layer routing with slidable and permutable terminals remains open if a net is allowed to have multiple terminals in a cluster.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient algorithms of wiring channels with movable terminals

The problem of wiring a channel of movable terminals in a VLSI chip is presented. Two subproblems are addressed: maximum alignment and wireable placement. Maximum alignment is to reassign terminal positions in the channel in order to maximize the number of nets that can be implemented as straight connections. Wireable placement is to find an assignment of the movable terminals to the vertical tracks in the channel that eliminates the vertical conflicts between nets. A restriction is imposed on the number of unconnected terminals in the maximum alignment problem to ensure that the number of columns in the channel is not increased in the process. The two subproblems are solved using two heuristic algorithms. Some well-known examples, including Deutsch's difficult example, are used as test cases. The results show that both channel width and via usage are reduced significantly by using the procedures. >

Boundary single-layer routing with movable terminals

The authors study a generalization of previous results on the boundary single-layer routing (BSLR) problem. In the BSLR problem, there is a planar graph, a collection of terminals on the boundary of the infinite face, and a set of multiterminal nets. A solution of BSLR consists of a set of vertex disjoint trees interconnecting the terminals belonging to the same (multiterminal) net. An algorithm, unifying and generalizing previous BSLR algorithms, to solve an arbitrary instance of BSLR, is presented. Problems involving slidable terminals (i.e. when terminals can slide within a certain range on the boundary) and permutable terminals (i.e. when positions of some terminals (going to the same gate) can be interchanged) are optimally solved. The proposed algorithm runs in O(e) time, where e is the number of edges in the input graph. The results are extended to handle gridless routing environments.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimal channel pin assignment

The authors study the channel pin assignment (CPA) problem subject to position constraints, order constraints, and separation constraints. The problem is to assign two sets of terminals to the top and the bottom of a channel to minimize channel density. It is shown that the problem is NP-hard in general and polynomial time-optimal algorithms are presented for a case where the relative orderings of the terminals on the top and the bottom of the channel are completely fixed. The problem of channel routing with movable modules is introduced, and it is shown that it is a special case of the CPA problem under the formulation, and can be solved optimally in polynomial time. How the algorithms can be incorporated into standard-cell and building-block layout systems is discussed. Experimental results indicate that substantial reduction in channel density can be obtained by allowing movable terminals.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Maximizing pin alignment in VLSI routing with movable terminals

Abstract This paper addresses a new problem of aligning two rows of movable terminals in order to minimize the channel width and via usage in the channel. The alignment problem of movable terminals is subject to the constraint that the number of vertical tracks used is not increased in the process. This constraint is not considerated in the paper referred to [6] which first considered the alignment problem of movable terminals. This problem is first shown to be NP‐complete, therefore, we present a heuristic algorithm. All examples presented in [2] including Deutsch's difficult example are used as the test routing problems. The programs were coded in C and implemented on SUN 3/110 workstation.

Via minimization in VLSI routing with movable terminals

A unified approach is developed for solving the general problem of minimizing the number of via holes in a two-layer very large-scale integration (VLSI) channel and switch-box routing environment with movable terminals. All horizontal segments of the nets are assumed to be in one layer, and the vertical segments in the other layer. Each net can have multiple terminals. Three different models are considered: (i) two-row channel routing, (ii) three-sided switch-box routing, and (iii) four-sided switch-box routing. The concept of a maximum parallel set of edges in a bipartite graph is introduced to solve the minimization problem. This leads to a unified graph-theoretic approach for solving the via minimization problem for all three models considered. The complexity of the proposed algorithm is O(N log N), in all three cases, where N is the number of pairs of terminals to be connected. >

Optimal Wiring of Movable Terminals

In this paper we consider the problem of local wiring in a VLSI chip. The problem is one of interconnecting two sets of terminals, one set on each side of a wiring channel, in accordance with a given interconnection pattern, and to accomplish this while minimizing some objective function. We make the further assumption that the terminals are not rigidly positioned and can be "moved" provided that this does not change the structural intent of the circuit. Several objective functions are considered-channel width, channel length, channel area, channel perimeter, number of via holes, as well as some constrained objective functions. For some of these objective functions, we are able to find polynomial time optimal algorithms while, for others, we prove NP-completeness and suggest efficient heuristics.