Motherboard Design Research Articles

SOC chip based smart window curtain design

Relying on the rapid development of embedded systems, it becomes possible to integrate the system hardware into the same chip, and the system on chip SOC (System on Chips) is therefore birthed. This paper will be based on the SOC hardware and software co-design and verification, through the design of intelligent curtains for the specific implementation design of a kind of application in the al-in-one multi-functional machine motherboard design, the motherboard control core using SOC chip, integrated two MCU units, through the main control screen to display the control information to achieve the intelligent window switching conversion switching through the key such as manual mode, timer mode, light control mode. This design uses Keil as the software writing platform to realize the SOC master control system based on the on-chip bus interconnection. As well as this design can effectively reduce the degree of system cumbersomeness and provide smart window design ideas.

PMFault: Faulting and Bricking Server CPUs through Management Interfaces

Apart from the actual CPU, modern server motherboards contain other auxiliary components, for example voltage regulators for power management. Those are connected to the CPU and the separate Baseboard Management Controller (BMC) via the I2C-based PMBus. In this paper, using the case study of the widely used Supermicro X11SSL motherboard, we show how remotely exploitable software weaknesses in the BMC (or other processors with PMBus access) can be used to access the PMBus and then perform hardware-based fault injection attacks on the main CPU. The underlying weaknesses include insecure firmware encryption and signing mechanisms, a lack of authentication for the firmware upgrade process and the IPMI KCS control interface, as well as the motherboard design (with the PMBus connected to the BMC and SMBus by default). First, we show that undervolting through the PMBus allows breaking the integrity guarantees of SGX enclaves, bypassing Intel’s countermeasures against previous undervolting attacks like Plundervolt/V0ltPwn. Second, we experimentally show that overvolting outside the specified range has the potential of permanently damaging Intel Xeon CPUs, rendering the server inoperable. We assess the impact of our findings on other server motherboards made by Supermicro and ASRock. Our attacks, dubbed PMFault, can be carried out by a privileged software adversary and do not require physical access to the server motherboard or knowledge of the BMC login credentials. We responsibly disclosed the issues reported in this paper to Supermicro and discuss possible countermeasures at different levels. To the best of our knowledge, the 12th generation of Supermicro motherboards, which was designed before we reported PMFault to Supermicro, is not vulnerable.

Highly configurable low cost remote laboratory with integrated support for learning â?? Hardware design

This paper presents a flexible and low cost design specification for a remote laboratory platform for electronics laboratories. The system utilises a motherboard design and this paper presents both the design of the motherboard, various designs for add on cards and shows how to configure the setup. The design is focused on providing the user with a combination of easy setup and a large freedom in reconfiguration all provided as a low cost solution. The solution is designed to facilitate a natural flow in the creation of all forms of remote laboratories, from the prototyping level up to a permanent installation. This motherboard has connector for both configuration cards, programmable and static as well as for standardized add-on boards for all the configurable components in the laboratory circuit. Acquisition hardware can easily be changed both during development and after the creation of the lab.

DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design. To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used. We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology. Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate >1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.

A performance guarantee heuristic for electronic components placement problems including thermal effects

In this work, Benders decomposition algorithm is used to deal with a computer motherboard design problem. Amongst all the possible formulations for the component placement problem, the chosen one creates an instance of the extensively studied Quadratic Assignment Problem ( QAP). This problem arises as a great challenge for engineers and computer scientists. The QAP inherent combinatorial structure makes the most efficient optimization algorithms to exhibit low performance for real size instances. It is also considered here the important addition of linear costs. This approach is directly responsible for the performance gain presented by our decomposition method. Coupled with the placement problem, it is under investigation the maximum temperature rising on the board surface. In order to solve the Energy Conduction Equation the Finite Volume Method is implemented, becoming possible to derive a secondary quality solution criterion. A set of test instances is then solved and the corresponding results are reported.

Cost effectiveness of ergonomic redesign of electronic motherboard

A case study to illustrate the cost effectiveness of ergonomic redesign of electronic motherboard was presented. The factory was running at a loss due to the high costs of rejects and poor quality and productivity. Subjective assessments and direct observations were made on the factory. Investigation revealed that due to motherboard design errors, the machine had difficulty in placing integrated circuits onto the pads, the operators had much difficulty in manual soldering certain components and much unproductive manual cleaning (MC) was required. Consequently, there were high rejects and occupational health and safety (OHS) problems, such as, boredom and work discomfort. Also, much labour and machine costs were spent on repairs. The motherboard was redesigned to correct the design errors, to allow more components to be machine soldered and to reduce MC. This eliminated rejects, reduced repairs, saved US $581,495/year and improved operators’ OHS. The customer also saved US $142,105/year on loss of business.

Exact analytical model for the AEP of control signals

An exact analytical model for the aliasing error probability (AEP) in the signature analysis of control signals using a modified signature analyser presented. The signature analyser used comprises a general-structure two-input compacting module (TICM), which simplifies the motherboard VLSI design by providing a flexible geometry, which could be easily integrated with neighbouring structures. The use of the modified data probe eliminates the ambiguity introduced by the high-impedance state and at the same time retains the same signature of the binary stream. The model specifies algebraically the effects of the TICM architecture, the test pattern length, and the control stream error probabilities. It is proved that the (hardware) criterion used for calculating the AEP for the internal- and external exclusive-OR two-input shift registers is not valid for the general case and a new criterion is provided. The results obtained are augmented by two special cases, a case study, and associated simulation.