MOSIS Foundry Research Articles

Lorenz-based chaotic cryptosystem: a monolithic implementation

A monolithic implementation of a cryptosystem based on the Corron and Hahs (1997) scheme is hereby presented. The baseband chaotic encryption/decryption system has been designed at the transistor level and fabricated using AMI 1.2 /spl mu/m CMOS technology available through the MOSIS foundry. While the mathematical model of the Lorenz system is straightforward, its silicon implementation is not. Typical circuit design considerations need to be considered such as the system's dynamic range, internal signal processing mode and basic building blocks all with the intent to provide an optimal design. This work addresses in detail: (1) practical design considerations of the cryptosystem and (2) actual measurement results that verify theoretical findings.

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

Development of master CMOS test vehicle chip for space radiation effect studies using CAMD X-ray synchrotron radiation

Abstract A master CMOS test vehicle chip using currently available CMOS technologies from MOSIS Foundry has been designed for use in monitoring electrical performance of CMOS based systems on board in space flights against the total dose effect. The master test chip includes designs of selected CMOS devices and logic circuits to monitor in an integrated manner the behavior of several radiation sensitive parameters namely, I – V characteristics, speed-power product, propagation delay time and fan-out capability, CMOS latchup, hot-carrier-induced charge effects in VLSI switching circuits and critical logic path through the functional logic device by a dynamic shift register. A methodology to evaluate test vehicle chip is proposed incorporating experimental studies, analytical modeling and their correlation with the experimental data. CMOS test chip fabricated from MOSIS Foundry wil be probed for static and dynamic data acquisition under preirradiated and postirradiated conditions and simulated operating environment. Space radiation exposure to the test devices will be simulated using Louisiana State University, Baton Rouge Center for Advanced Microstructures and Devices (CAMD) X-ray synchrotron as a radiation source #1 .