MOSFET Diode Research Articles

Discontinuous-Current Mode Operation of a Two-Phase Interleaved Boost DC–DC Converter With Coupled Inductor

A two-phase interleaved boost dc–dc converter with an inversely coupled inductor in a discontinuous-current mode (DCM) is analyzed by the equivalent inductance method. Coupling effects on the circuit statuses are described, and a forced conduction of the power diode or reverse-paralleled diode of MOSFET is caused by coupling. As a result, three major circuit statuses are figured out according to the physical relationship between the input–output voltage ratio and the coupling coefficient, and their condition boundaries are used to classify the DCM operation modes. Then, considering the load (duty cycle) variation, ten DCM operation modes are comprehensively analyzed. The analysis can be used to make an easy prediction of operation modes, and extended to the analysis of an interleaved buck converter or buck/boost bidirectional converter with a coupled inductor in DCM. At last, a 300-W prototype is built and tested in the lab to verify the analysis.

Demonstration of SiC-MOSFET Embedding Schottky Barrier Diode for Inactivation of Parasitic Body Diode

External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.

A novel high efficiency CMOS RF/DC power harvester based on constant on/off time buck controller for 60GHz frequency band

A novel 60 GHz RF/DC power harvesting system is presented. The system consists of RF to DC rectifier and a DC/DC Buck converter based on constant ON/OFF time (COOT) control. The rectifier has a structure of voltage doubler, but employs diodes that have lower parasitics compared to those of the standard MOSFET diodes, resulting in improved power conversion efficiency. The peak efficiency of the rectifier obtained with the extracted parasitics for the output power of 1 mW is about 25%. In order to keep the output voltage of the system to 1.2 V, the COOT control in the Buck converter is used. COOT control has much better efficiency at low output powers compared to the PWM systems. For correct operation of the COOT control, auxiliary sub-blocks: a low power high-speed comparator, a hysteresis comparator, and a high-speed voltage reference are designed and presented. The maximum switching frequency in the Buck converter is about 100MHz and the whole control system has very low static power consumption. The efficiency of the overall system for the output power of 1mW is about 21%. The system is designed in 65 nm CMOS technology.

High-Efficiency Single-Phase AC–AC Converters Without Commutation Problem

This paper proposes single-phase direct pulsewidth modulation (PWM) buck-, boost-, and buck–boost-type ac–ac converters. The proposed converters are implemented with a series-connected freewheeling diode and MOSFET pair, which allows to minimize the switching and conduction losses of the semiconductor devices and resolves the reverse-recovery problem of body diode of MOSFET. The proposed converters are highly reliable because they can solve the shoot-through and dead-time problems of traditional ac–ac converters without voltage/current sensing module, lossy resistor–capacitor ( RC ) snubbers, or bulky coupled inductors. In addition, they can achieve high obtainable voltage gain and also produce output voltage waveforms of good quality because they do not use lossy snubbers. Unlike the recently developed switching cell (SC) ac–ac converters, the proposed ac–ac converters have no circulating current and do not require bulky coupled inductors; therefore, the total losses, current stresses, and magnetic volume are reduced and efficiency is improved. Detailed analysis and experimental results are provided to validate the novelty and merit of the proposed converters.

A 0.7 V Relative Temperature Sensor With a Non-Calibrated <formula formulatype="inline"><tex Notation="TeX">$\pm 1~^{\circ}{\rm C}$</tex></formula> 3<formula formulatype="inline"><tex Notation="TeX">$\sigma$</tex></formula> Relative Inaccuracy

This paper presents a new low-voltage relative temperature sensor for multi-core digital processor on-chip thermal management in a 180 nm CMOS process. Three types of sensing diodes including Schottky barrier diode (SBD), subthreshold MOSFET diode and dynamic threshold MOSFET (DTMOS) diode have been investigated for low-voltage operation, while traditional parasitic PNP-bipolar junction transistor (BJT) diodes are implemented to provide a performance reference. A matrix of 7 $\times$ 7 small remote sensor nodes is implemented on the chip with a deployment density of 49/0.81 ${\rm mm}^{2}$ and sharing the same bias current generator, control logic, and data converter. The measured minimum supply voltage (not including the clock control block) of the sensor is 0.7 V over $-55~^{\circ}{\rm C}$ to 125 $~^{\circ}{\rm C}$ . The relative sensing inaccuracies $(3\sigma)$ without calibration are less than $\pm 1.5~^{\circ}{\rm C}$ , $\pm 1.2~^{\circ}{\rm C}$ and $\pm 1~^{\circ}{\rm C}$ for the designs based on SBD, subthreshold MOSFET, and DTMOS, respectively. To the best of the authors’ knowledge, this is the first time that non-calibrated relative sensing accuracy is reported for SBD-based and DTMOS-based temperature sensors, and the best reported result for the design based on subthreshold MOSFET. The absolute inaccuracies with calibration-per-chip are also presented. Furthermore, the multi-location thermal monitoring function has been experimentally demonstrated and a 1.8 $^{\circ}{\rm C/mm}$ on-chip temperature gradient was detected.

Corrigendum

Choi H, Kim MG, Cumins TM, Hwang JY, Shung KK. Power MOSFET–diode–based limiter for high-frequency ultrasound systems. Ultrason Imaging. 2014;36:317-330. Original DOI: 10.1177/0161734614524180 In this article, published in the October 2014 issue, the affiliation of the corresponding author Hojong Choi has been changed. Following is his revised affiliation: Hojong Choi, Department of Medical IT Convergence Engineering, Kumoh National Institute of Technology, Gumi, Gyeongbuk, South Korea Email: hojongch@kumoh.ac.kr

Power MOSFET–Diode–Based Limiter for High-Frequency Ultrasound Systems

The purpose of the limiter circuits used in the ultrasound imaging systems is to pass low-voltage echo signals generated by ultrasonic transducers while preventing high-voltage short pulses transmitted by pulsers from damaging front-end circuits. Resistor-diode-based limiters (a 50 Ω resistor with a single cross-coupled diode pair) have been widely used in pulse-echo measurement and imaging system applications due to their low cost and simple architecture. However, resistor-diode-based limiters may not be suited for high-frequency ultrasound transducer applications since they produce large signal conduction losses at higher frequencies. Therefore, we propose a new limiter architecture utilizing power MOSFETs, which we call a power MOSFET-diode-based limiter. The performance of a power MOSFET-diode-based limiter was evaluated with respect to insertion loss (IL), total harmonic distortion (THD), and response time (RT). We compared these results with those of three other conventional limiter designs and showed that the power MOSFET-diode-based limiter offers the lowest IL (-1.33 dB) and fastest RT (0.10 µs) with the lowest suppressed output voltage (3.47 Vp-p) among all the limiters at 70 MHz. A pulse-echo test was performed to determine how the new limiter affected the sensitivity and bandwidth of the transducer. We found that the sensitivity and bandwidth of the transducer were 130% and 129% greater, respectively, when combined with the new power MOSFET-diode-based limiter versus the resistor-diode-based limiter. Therefore, these results demonstrate that the power MOSFET-diode-based limiter is capable of producing lower signal attenuation than the three conventional limiter designs at higher frequency operation.

A CMOS AC/DC charge pump for a wireless sensor network

An AC/DC charge pump implemented with MOS FETs has been presented for wireless sensor network applications. The proposed AC/DC charge pump can generate a stable output with low power dissipation and high pumping efficiency, which has been implemented in 0.13 μm CMOS technology. The proposed charge pump employs MOSFET diodes with low thresholds, and improves the conversion efficiency. The analytical model of the voltage multiplier, the simulation results, and the chip testing results are presented.

Nonisolated Bidirectional DC–DC Converters With Negative-Coupled Inductor

A novel solution for nonisolated bidirectional dc-dc converters (NI-BDCs) with advantages of simple topology, high efficiency, and high reliability is proposed. A small negative-coupled inductor (NCI) is employed to split the switch branch in the NI-BDC into two power flows clearly and prevent the freewheeling current from flowing through the body diode of MOSFET. As a result, the reverse-recovery problem of the MOSFET's body diode is alleviated. The topology method is presented and a family of NI-BDCs with NCI is proposed. The idea is further extended to a positive-coupled-inductor (PCI) solution by merging the NCI and the filter inductor into a PCI. And a family of NI-BDCs with PCI is proposed. The key operational principle and design consideration are presented with experimental results given.

Super-linear rectifying property of rubrene single crystal devices

We have observed a rectifying behavior in a lateral symmetrical device structure based on rubrene single crystals. Our analysis shows that the rectifying characteristics are not due to formation of Schottky junction between the electrode and the organic semiconductor, but should be attributed to a mechanism that is similar to the super-linear operation regime in organic field-effect transistors. Furthermore, we have demonstrated that this rectifying behavior can be turned on and off via modulation of the density of space charge in the organic semiconductor/substrate interface, which essentially affects the threshold voltage ( V T). Our results demonstrate a simple approach that can potentially be used to fabricate organic rectifiers without application of multi-layer device structure such as MOSFET diode.

A 17 GHZ colpitts VCO using reverse‐ and forward‐biased diode tuning in 0.18 μm CMOS

AbstractA 17 GHz complementary Colpitts voltage‐controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The drain‐body diode of MOSFET is used as the varactor. The VCO consists of two single‐ended complementary Colpitts LC‐tank VCOs coupled by a pair of capacitors. At the supply voltage of 1.2 V, the output phase noise of the VCO is −108.54 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 17.3 GHz, and the figure of merit is −189.51 dBc/Hz. Total VCO core power consumption is 2.4 mW. Tuning range is about 1 GHz, from 17.4 to 16.4 GHz, whereas the control voltage was tuned from 0 to 0.9 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 38–41, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24818

Study of Dopant Redistribution at the Substrate-Source/Drain p-n Junction of Nanoscale MOSFET During Progressive Breakdown

During the evolution of dielectric breakdown (BD) in MOSFETs, the substantial localized temperatures (which could exceed the silicon melting point) in the vicinity of the BD spot may cause dopants at the source/drain (S/D) to be redistributed (IEDM Tech. Dig., p. 717, 2004; IEEE Proc. IPFA, p. 131, 2005). The preliminary study of dopant redistribution based on the diode current-voltage (I-V) characteristics at the substrate-S/D p-n junction of a BD MOSFET was presented by Lim (IEEE Proc. IPFA, p. 131, 2005). The post-BD MOSFET diode current measured in the reverse bias as well as the low-voltage region of the forward bias was found to increase significantly as progressive BD evolves. The simulation results associated with the dopant redistribution are in good agreement with the experimental measurements. This confirms that the dopant redistribution is one of the dominant mechanisms responsible for the change in the post-BD MOSFET diode I-V characteristics. In addition, the dopant redistribution in a large-area long-channel BD MOSFET is found to be a function of BD location. However, the BD location dependence of the dopant redistribution will vanish in a narrow short-channel BD MOSFET

Measurement of the BJT activation current during the reverse recovery of power MOSFET's drain-source diode

A new and simple method to measure the activation current of the parasitic BJT in the drain-source MOSFET's diode is presented. Based on the evaluation of the stored charge at supply voltages lower than the maximum reverse voltage of the device, accurate and safe measurements have been performed at forward current levels up to the MOSFET's maximum current rating.

MOSFET diode as a feedback reset element on charge amplifiers

A MOSFET, connected as a diode with gate and drain short circuited and biased in saturation mode, is proposed as a substitute for the high-value feedback resistor to provide dc feedback and signal reset in integrated charge amplifiers with BJT input transistors. This paper describes the MOSFET design rules to set the desired value of the discharge time constant, to minimize its noise contribution, and to operate it in a low voltage circuit. The behavior of the MOSFET as an almost fixed value resistor is evidenced by the single time-constant discharge of the signal at the output of a prototype preamplifier for fast (<50 ns) shaping, whose experimental noise performance is also reported.

Trends in advanced process technology—Submicrometer CMOS device design and process requirements

Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a beating on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. MOSFET diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-µm calls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that downsizing will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary.