MOS Transistor In Saturation Research Articles

A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter

A new resistorless linear voltage-to-current converter (VCC) utilizing ten MOS transistors is described. The circuit uses saturated MOS transistors with different threshold voltages to produce an output current that is linearly related to the input voltage. The compensation of high-order nonlinear errors is also presented. The VCC has been fabricated using a 0.18- $\mu\mbox{m}$ standard CMOS technology. Measured results show that the proposed VCC achieves nonlinearity of less than ±2.2% in the input voltage range of 1.3–3 V with maximum power consumption of 0.21 mW and effective chip area of 2200 $\mu \mbox{m}^{2}$ .

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

SummaryIn this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.

± 1V high frequency four quadrant current multiplier

A high frequency four quadrant current multiplier is presented. The current multiplier uses complementary MOS devices in the triode region and exploits the square-law behaviour of saturated MOS transistors. The circuit operates using the supply voltages of±1V. The cutoff frequency is 1.74 GHz with a total harmonic distortion less than 0.065 % (at 1 MHz). The power dissipation is 0.85 mW.

MOS Translinear Principle for All Inversion Levels

In this brief, we derive a translinear principle for alternating loops of saturated MOS transistors that is valid at all levels of inversion starting from a simplified version of the Enz-Krummanacher-Vittoz model of the MOS transistor. This generalized translinear principle reduces to the conventional one when all transistors in a translinear loop are biased in weak inversion and it reduces to the voltage-translinear principle when all transistors in the loop are biased in strong inversion. We show experimental measurements from an alternating loop of four nMOS transistors that was fabricated in a 0.5-mum CMOS process through MOSIS to corroborate the generalized translinear principle. Finally, we discuss some potential applications of the principle.

Analogue motion estimation based upon a squaring circuit

Motion estimation (ME) is the most computationally demanding part of the digital video coding process. The use of analogue computational circuits in this application can offer reductions in size and power dissipation. However, analogue circuits are subject to variations which can reduce performance. In this paper the analogue non-idealities are considered, and results are presented for video conferencing applications. Furthermore, a compact MOS squaring circuit for use in analogue ME processors is proposed. The circuit makes use of the inherent square-law characteristic of the MOS transistor in saturation and features small area, low-power and low-voltage operation. Measurements from fabricated samples of the circuit were incorporated in system-level simulations. The results of the simulations confirmed the suitability of the circuit for the intended application.

Low-power CMOS integrated circuits for radio frequency applications

This paper presents results for a mixer, two voltage-controlled oscillators (VCOs) and a frequency doubler (FD) suitable for low-power CMOS radio frequency (RF) systems. Results are first described for a mixer which uses the body terminal of the transistor as one of the inputs to down-convert a 1.9 GHz RF signal to a 250 MHz intermediate-frequency signal. Next, two VCOs are described. The first VCO is an ultra-low-power oscillator designed to operate in the 2.4 GHz industrial scientific medical band with a supply of 0.4 V. The second VCO described is a fully integrated LC-tank VCO with automatic amplitude control operating at 4 GHz. Frequency tuning for this VCO is performed by accessing the body of cross-coupled transistors of the VCO core. Finally, a wideband, low-power implementation of a frequency doubler is presented. The frequency doubler consists of two identical unbalanced source-coupled pairs with different W/L ratios, whose inputs are connected in parallel and its output taken single-ended. The FD is based on the MOS transistor in saturation. All circuits were designed in a deep n-well 0.18 /spl mu/m technology, allowing application of different potentials to the body of different NMOS transistors.

Current-mode full-wave rectifier and vector summationcircuit

A current-mode full-wave rectifier and current-mode vector summation circuit are presented. They are implemented by utilising the square-law characteristics of MOS transistors in saturation. A two-input vector summation circuit using the proposed full-wave rectifier has been fabricated in a 0.8 /spl mu/m CMOS process. The experimental and simulation results confirm the feasibility of the proposed circuits.

Low-voltage CMOS four-quadrant analogue multiplierfor RF applications

A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture.

Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I–V converters, a current mirror and four matched transistors to achieve a transresistance gain of 73 dBΩ, a –3 dB bandwidth of 4.3 MHz, a total harmonic distortion below 1% and a maximum power dissipation of 130 µW. Design guidelines have been set to link the circuit performance, in terms of the gain, the input operating range, the fabrication area, and the device aspect ratios, to key device and technology parameters. The scope for further performance improvement using BiCMOS is also highlighted. The experimental results obtained from the chip were found to be in close agreement with the simulated results.

Extending the functionality of a flexible current-modeCMOS circuit

A current-mode cell based on the square-law characteristic of MOS transistors in saturation is revisited to extend its functionality. The original structure was reported to provide a squaring operation. However, by biasing the circuit differently the circuit can perform the inverse operation and operate as a geometric-mean/square-rooter. This is illustrated with experimental results. >

A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor

For reasons related to layout, processing, or hot-carrier stressing, a MOSFET may have unequal source and drain parasitic resistances. In such cases, it is important to accurately extract the asymmetry in these resistances, without depending on individual judgments. In this brief, we present a simple method to extract this asymmetry. This method is based on an accurate formulation and measurement of the ac conductances with respect to the gate terminal of an MOS transistor in saturation. >

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 /spl mu/m CMOS process. Experimental results obtained from it are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New high-compliance CMOS current mirror with low harmonic distortion for high-frequency circuits

A new low-distortion high-compliance CMOS current mirror is presented. The large-signal nonlinear characteristic of MOS transistors in saturation, combined with capacitances present in current mirror circuits, causes harmonic distortion. This effect is explained for a well-known current mirror circuit, and the new circuit is described which substantially reduces harmonic distortion while using only one extra standard process component.

CMOS floating voltage-controlled negative resistor

A circuit technique for realising a floating voltage-controlled negative resistor that is suitable for fabrication in CMOS technology is presented. The negative resistor action is achieved through nonlinearity cancellation of the currents of MOS transistors in saturation.

Two quadrant analogue squarer circuit based on MOS square-law characteristic

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.

A CMOS analog continuous-time delay line with adaptive delay-time control

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections. >

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits.

Simple two-sections model for short channel MOS transistors in saturation

The paper presents a model for short channel MOSFETs based on a new empirical formula for the drain current in saturation. The model guarantees the continuity of the transconductance, the output conductance and its derivatives at the transition from the triode to the saturation region, while taking into account some important second-order effects. The theoretical predictions of the model are found to be in excellent agreement with experimental data.

A simple model for the MOS transistor in saturation

A model is proposed that takes into account mobility reduction, carrier velocity saturation effects and length modulation for an NMOS transistor. The model ensures continuity of output conductance and its derivative with respect to the drain voltage at the onset of saturation and is made simple by the use of empirical formulas for the drain current in both linear and saturation regions.

Study of saturation conduction in short-channel MOS transistors by numerical simulation

The potential and current density distribution in a short-channel MOS transistor in saturation has been studied in detail by numerical simulation. The pushing effect of carriers from the surface in the draincontrolled region is discussed by introducing a field depth parameter. The pinch-off condition of the channel is examined: at gate voltages below a transition voltage Vtr, the length of the pinch-off region is determined by the pushing of carriers away from the surface; whereas at higher gate voltages, it is determined by the velocity saturation of carriers. An analytical formula for the length of the pinch-off region at gate voltages below Vtr is derived based on simulation results.