MOS Current-mode Logic Gates Research Articles

Simple and Accurate Model for the Propagation Delay in MCML Gates

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively.

A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation. The approach has been validated with post-layout simulations considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. In particular, OR/NOR gates with 3, 4, and 5 inputs implemented both with the conventional 2-inputs MCML gates implementation ( Fin2) and the proposed MF MCML have been compared. Results show a reduction in the power consumption of the MF MCML equal to 3/4, 2/3 and 5/8 for the OR3, OR4 and OR5 logic functions respectively. Moreover, in terms of speed the Fin2 implementation has a delay at least 1.4 worst than the MF MCML, but is generally 1.7 worst than the proposed MF MCML gate. In this paper we have presented a novel approach which allows to implement MCML gates with a fan-in higher than 2 while keeping the minimum supply voltage as low as the one of a conventional MCML inverter. The proposed methodology, named Multi Folded MCML, born out by a generalization of the Folded MCML previously proposed by authors. The approach has been compared against the conventional Fin2 implementation (suited to implement arbitrarily logic function with a low power supply) both in terms of power consumption and propagation delay. The results have clearly demonstrated the advantages provided by the MF MCML. In particular, OR/NOR gates with 3-, 4-, and 5-inputs have been compared considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. Post layout simulation results have shown that the MF gates outperform the conventional implementations in terms of propagation delay for all the considered logic functions. In particular, the propagation delay of the Fin2 implementation has been shown to be at least 1.4 times higher than the one of the MF MCML implementation and even 2 times higher for other logic functions. The power consumption of the MF gates has been shown to be 3/4 , 2/3 and 5/8 than the one of the Fin2 implementations for the OR3 , OR4 and OR5 logic functions respectively. Hence, the only drawback of the propose techniques seems due to a more complex design procedure.

An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization

MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> number of logic gates, the proposed mathematical program has reduced the number of variables to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> +1, in comparison to 7 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> +1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-μm CMOS technology.

Nanopower Subthreshold MCML in Submicrometer CMOS Technology

This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW.

Bulk-drain connected load for subthreshold MOS current-mode logic

Bulk-drain connected PMOS transistors are proposed as loads for subthreshold MOS current-mode logic gates. Such loads exhibit an approximately linear dependence of the subthreshold drain-source current on the drain-source voltage, guaranteeing robust gate operation. The design and performance of an inverter gate and ring oscillator in a 0.25 mum CMOS technology are presented

Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers

A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the power-delay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18-mum CMOS process