Montgomery Scalar Multiplication Research Articles

Differential addition on binary elliptic curves

This paper presents new and fast differential addition (i.e., the addition of two points with the known difference) and doubling formulas, as the core step in Montgomery scalar multiplication, for various forms of elliptic curves over binary fields. The formulas are provided for binary Edwards, binary Hessian and binary Huff elliptic curves with cost of 5M+4S+1D when the given difference point is in affine form. Here, M,S,D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In this paper, we show that every ordinary elliptic curve E over binary field F2n has Lopez and Dahab differential addition and doubling formulas with suitable function. This paper also presents, new complete differential addition formulas for binary Edwards curves with cost of 5M+4S+2D. Also, new complete Montgomery ladder and scalar multiplication algorithms are presented using the complete differential addition formulas.

Speeding up regular elliptic curve scalar multiplication without precomputation

This paper presents a series of Montgomery scalar multiplication algorithms on general short Weierstrass curves over fields with characteristic greater than 3, which need only 12 field multiplications per scalar bit using 8 $ \sim $ 9 field registers, thus outperform the binary NAF method on average. Over binary fields, the Montgomery scalar multiplication algorithm which was presented at the first CHES workshop by López and Dahab has been a favorite of ECC implementors, due to its nice properties such as high efficiency (outperforming the binary NAF), natural SPA-resistance, generality (coping with all ordinary curves) and implementation easiness. Over odd characteristic fields, the new scalar multiplication algorithms are the first ones featuring all these properties. Building-blocks of our contribution are new efficient differential addition-and-doubling formulae and a novel conception of on-the-fly adaptive coordinates which varies in accordance with not only the base point but also the bits of the given scalar.

An Efficient Usage Indian Vedic Shrewdness in Multiplication Module of ECC Co-Processor Architecture

Elliptic Curve Cryptography (ECC) becomes an apparent choice when the security, speed, key length and area constraints are exhorted. This paper implements the ECC over GF(2256) based on the Montgomery scalar multiplication in a field programmable gate array (FPGA) processor with the focus of minimizing the resource binding with random sequence supported by linear feedback shift register (LFSR). Multiplier is most used components of such co-processors and hence even a productive multiplier can save the resource in large extend. This paper employs an efficient multiplier devised from the ancient Indian “Vedic Mathematic Sutras”. The most efficient sutra called “Urdhva Tiryakbhayam” paves a speedy, vertical and crosswise, digital platform supportive and reversible logic implementable multiplier. The proposed ECC processor performs the 256 bit point multiplication with the power consumption of 691mW and utilizes 13918 LUTs for 100 MHz frequency when implemented in a Spartan 3E-XC3S1600E using Modelsim 5.7 and Xilinx 9.2i.

단순 전력분석 공격에 대처하는 타원곡선 암호프로세서의 하드웨어 설계

In this paper hardware implementation of GF(2 191 ) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF(2m ), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.