Monolithic Processor Research Articles

L24

Networks of sensors must process large amounts of intermittently-available data in situ. This motivates the investigation of means for achieving high performance when required, but ultra-low-power dissipation when idle. One approach to this challenge is the use of embedded multiprocessor systems, leading to trade-offs between parallelism, performance, energy efficiency, and cost. To evaluate these trade-offs and to gain insight for future system designs, this article presents the design, implementation, and evaluation of a miniature, energy-scalable, 24-processor module, L24 , for use in embedded sensor systems. Analytic results and empirical evidence motivating such embedded multiprocessors is provided, and a parallel fixed-point fast Fourier transform implementation is presented. This application is used as a challenging but realistic evaluator of the presented hardware platform. Through a combination of hardware measurements, instruction-level microarchitectural simulation, and analytic modeling, it is demonstrated that the platform provides idle power dissipation over an order of magnitude lower than systems employing a monolithic processor of equivalent performance, while dynamic power dissipation remains competitive. Taking into account both application computation and interprocessor communication demands, it is shown that there may exist an optimum operating voltage that minimizes either time-to-solution, energy usage, or the energy-delay product. This optimum operating point is formulated analytically, calibrated with system measurements, and evaluated for the hardware platform and application presented.

Parallelism, Performance, and Energy-Efficiency Tradeoffs for In Situ Sensor Data Processing

The in situ processing of vast amounts of data, available intermittently in networks of sensors, motivates investigation of means for achieving high performance when required, but ultralow-power dissipation when idle. One approach is the use of embedded multiprocessor systems, leading to tradeoffs between parallelism, performance, energy-efficiency, and cost. To evaluate these tradeoffs, and to gain insight for future system designs, this letter presents the design, implementation, and evaluation of a miniature, energy-scalable, 24-processor module, L24, for compute-intensive in situ sensor data processing tasks. The platform provides idle power dissipation over an order of magnitude lower than systems employing a monolithic processor of equivalent performance, while dynamic power dissipation remains competitive. Taking into account both application computation and interprocessor communication demands, it is shown that there may exist an optimum operating voltage that minimizes either time-to-solution, energy usage, or the energy-delay product. This optimum operating point is formulated analytically, calibrated with system measurements and instruction-level microarchitectural simulation, and evaluated for the hardware platform and application presented.

Chip multi-processor scalability for single-threaded applications

The exponential increase in uniprocessor performance has begun to slow. Designers have been unable to scale performance while managing thermal, power, and electrical effects. Furthermore, design complexity limits the size of monolithic processors that can be designed while keeping costs reasonable. Industry has responded by moving toward chip multi-processor architectures (CMP). These architectures are composed from replicated processors utilizing the die area afforded by newer design processes. While this approach mitigates the issues with design complexity, power, and electrical effects, it does nothing to directly improve the performance of contemporary or future single-threaded applications.This paper examines the scalability potential for exploiting the parallelism in single-threaded applications on these CMP platforms. The paper explores the total available parallelism in unmodified sequential applications and then examines the viability of exploiting this parallelism on CMP machines. Using the results from this analysis, the paper forecasts that CMPs, using the "intrinsic" parallelism in a program, can sustain the performance improvement users have come to expect from new processors for only 6-8 years provided many successful parallelization efforts emerge. Given this outlook, the paper advocates exploring methodologies which achieve parallelism beyond this "intrinsic" limit of programs.

Dedicated optoelectronic stochastic parallel processor for real-time image processing: motion-detection demonstration and design of a hybrid complementary-metal-oxide semiconductor– self-electro-optic-device-based prototype

We report experimental results and performance analysis of a dedicated optoelectronic processor that implements stochastic optimization-based image-processing tasks in real time. We first show experimental results using a proof-of-principle-prototype demonstrator based on standard silicon-complementary-metal-oxide-semiconductor (CMOS) technology and liquid-crystal spatial light modulators. We then elaborate on the advantages of using a hybrid CMOS-self-electro-optic-device-based smart-pixel array to monolithically integrate photodetectors and modulators on the same chip, providing compact, high-bandwidth intrachip optoelectronic interconnects. We have modeled the operation of the monolithic processor, clearly showing system-performance improvement.

Associative controlling of monolithic parallel processor architectures

The VLSI implementation of monolithic parallel processor architectures is supported by the ongoing progress of semiconductor technology. Nevertheless, a cost efficient realization of flexible parallel processors, suitable for a broad range of video processing applications, requires efficient schemes for controlling of the provided parallel data paths. Therefore, a novel associative controlling scheme is presented. This approach enables an efficient implementation of monolithic parallel processors at reasonable hardware cost. The paper presents performance data of associative controlling based on a simplified model in comparison to alternative controlling schemes, like SIMD, MIMD, SPMD, and MSIMD. Furthermore, an overview of the architecture of the currently developed associatively controlled PRISMA video signal processor is given. >

A CORDIC Arithmetic Processor Chip

A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addition to the menu of hyperbolic and linear operations, is a relatively trivial matter, in terms of both hardware cost and execution time. A bulk CMOS technology with conservative layout rules is used for the sake of high reliability, low-power consumption, and good cycle speed.

A Cordic Arithmetic Processor Chip

A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addition to the menu of hyperbolic and linear operations, is a relatively trivial matter, in terms of both hardware cost and execution time. A bulk CMOS technology with conservative layout rules is used for the sake of high reliability, low-power consumption, and good cycle speed.