Monolithic Active Pixel Sensor Prototype Research Articles

Energy calibration through X-ray absorption of the DECAL sensor, a monolithic active pixel sensor prototype for digital electromagnetic calorimetry and tracking

In calorimetry, the predominant detection principle is to measure the energy deposited by particles within a shower initiated by an incident particle. An alternative concept is a sampling calorimeter where the highly granular active layers rather measure the number of secondary particles in the shower by detecting hits through binary readout similar to sensors for tracking applications. In this context, the DECAL sensor is a fully-depleted monolithic active pixel sensor prototype with reconfigurable readout for digital electromagnetic calorimetry and tracking. Its 64 × 64 pixels with a pitch of 55 µm are fabricated in a modified TowerJazz 180 nm CMOS imaging process using a 25 µm epitaxial silicon layer. The readout at 40 MHz is configurable in counting hits in the sensor grouped as either 64 strips or 4 pads. In this article, we present the energy calibration of this sensor using a gamma source of americium-241 as well as X-ray fluorescence at various wavelengths. The uniformity of the pixel responses is shown, allowing the summation of counts across all pixels. By that, two standalone energy calibration methods are developed that describe the X-ray absorption in the energy range of 4–60 keV and agree with each other. The signal pulse height is related to the absorbed photon energy with a 5.54 ± 0.37 mV/keV scale which corresponds to a conversion gain of cg = 19.95 ± 1.32 μV/e−. The relative energy resolution for photon absorption is found to be σE/E = 11.8 ± 3.0%. The absolute counts observed with the DECAL sensor agree with expectations and substantiate the assumption of a fully depleted epitaxial layer. The understanding of the photon absorption is an important input for further development of the sensor towards a multi-layer calorimeter.

Characterization of a CMOS Pixel Sensor prototype for the CEPC vertex detector

The proposed Circular Electron Positron Collider poses significant challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor prototype, named TaichuPix, has been developed based on a column drain readout architecture. The performance of the second version of this prototype, TaichuPix2, has been evaluated using a radioactive source, which exhibits a time walk of less than 100ns corresponding to the threshold of 380 e− and amplitude variation of analog output from 300mV to 500mV. An infrared laser setup is utilized to estimate the single-point spatial resolution of this sensor for minimum-ionizing particles. The setup includes a high-precision three-dimensional translation stage and an optical system with a 1064nm laser diode. With this setup, the spatial resolution is estimated to be about 4µm. The performance for real particles is to be confirmed in a test beam.

Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology

The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results.

Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology

A series of monolithic active pixel sensor prototypes (APTS chips) were manufactured in the TPSCo 65 nm CMOS imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4 × 4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel pitches (10 µm–25 µm), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements.

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection mechanism using a radioactive source. These results prove that the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify that it can work up to about 3 Gbps, while they also indicate that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

Design and initial characterization of MIC4, the monolithic active pixel sensor prototype for CEPC vertex detector

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs factory to produce adequate events, which are the basis for high-precision measurements of the Higgs boson. The vertex detector in the CEPC should meet the requirements of a low material budget, high spatial resolution, fast readout speed and low power consumption. A monolithic active pixel sensor (MAPS) has been selected as the most promising technology for the vertex detector. The MIC4 sensor is the first prototype developed within the preliminary R&D activities of the CEPC vertex detector. It has been implemented in the TowerJazz 180 nm CMOS image sensor (CIS) process. It measures 3.1 mm × 4.6 mm and features a 128 row × 64 column pixel array with a pixel pitch of 25μm. In this work, a binary front-end has been designed for a compact pixel combined with a sparsified readout circuitry. Each pixel is composed of an amplifier, a shaper, a discriminator and digital logic. A new asynchronous zero-suppression data-driven readout circuit architecture is proposed and implemented in MIC4. We have performed some initial tests on this chip and obtained detailed results. The front-end features a peaking time below 1μs, a shaping time less than 3μs, a charge threshold of approximately 100 e−, an average temporal noise (TN) of 6 e− and a fixed pattern noise (FPN) of 36 e−. The addresses of the fired pixels can be readout in the digital part of the chip at a clock running at 30 MHz with the new data-driven readout circuit architecture. The hit map under 55Fe X-ray exposure shows that the sensor designed in MIC4 works well. The probability of single event latch-up (SEL) σSEL is 1.02 × 10−6 cm2 at a linear energy transfer (LET) of 20.05 MeV cm2/mg.

Implantable CMOS pixel sensor for positron imaging in rat brain

IMIC is a Monolithic Active Pixel Sensor prototype designed for the MAPSSIC project, which aims at developing wireless intracerebral probes dedicated to image positron-emitting source activity in the brain of awake and freely moving rats. Former experiments with the PIXSIC positron probe based on a passive sensor have validated the proof of concept, but have also shown limitations with regards to the probe robustness and to its transparency to annihilation photons. The IMIC circuit features a matrix of 16 × 128 active pixels of 30 × 50 µm2 size and targets to overcome the PIXSIC probe drawbacks by exploiting a thin sensitive layer of 18 µm, still featuring an overall thickness close to 300 µm. Additionally, by using a low power (55 nW/pixel) in-pixel front-end architecture providing binary output, IMIC solves the challenge of implanting an active sensor in tissues where overheating is forbidden.The needle-shaped sensor 610 µm × 12000 µm was fabricated and tested in laboratory. The whole sensor dissipates 160 µW and its imaging capabilities were asserted with various sources: 55Fe, 90Sr and 18F. These tests also demonstrated robust count-rate measurement with IMIC in the range 10–1000 counts/matrix/s. Finally, a dedicated setup qualitatively confirmed excellent in-sensitivity to 511 keV γ-rays.In this paper, we present the sensor requirements and its detailed design. We also discuss the first characterisation results and the outlook for the integration of IMIC into an implantable probe.

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

The prototype of a three-dimensional (3D) monolithic active pixel sensor (MAPS) has been characterized. The device, featuring a 20μm pitch, was designed based on the same approach that was adopted in developing the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous tiers fabricated in a 130nm CMOS technology. Different kinds of test structures, including single pixels, 3×3 arrays and 8×8 and 16×16 matrices were tested. Functionality of the collecting deep N-well electrode, the analog front-end and the digital readout electronics has been demonstrated. Inter-tier communication was found to work properly in the case of redundant interconnection and could be exploited for the test of the analog pixel section. On the other hand, inter-tier interconnections based on individual bond pads were proven ineffective likely due to wafer misalignment.

Small-Scale Readout System Prototype for the STAR PIXEL Detector

A prototype readout system for the STAR PIXEL detector in the Heavy Flavor Tracker (HFT) vertex detector upgrade is presented. The PIXEL detector is a monolithic active pixel sensor (MAPS) based silicon pixel vertex detector fabricated in a commercial CMOS process that integrates the detector and front-end electronics layers in one silicon die. Two generations of MAPS prototypes designed specifically for the PIXEL are discussed. We have constructed a prototype telescope system consisting of three small MAPS sensors arranged in three parallel and coaxial planes with a readout system based on the readout architecture for PIXEL. This proposed readout architecture is simple and scales to the size required to readout the final detector. The real-time hit finding algorithm necessary for data rate reduction in the 400 million pixel detector is described, and aspects of the PIXEL system integration into the existing STAR framework are addressed. The complete system has been recently tested and shown to be fully functional.