Modular Multiplication Research Articles

An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.

An influence modelling and analysis method of reducing carbon emissions for mould forming processes in patternless sand casting

The foundry industry has gradually become an important concern for carbon emissions. The composite patternless casting, which combines sand mould 3D printing and sand mould milling technologies, is an effective way to explore the potential of energy saving and emission reduction in the foundry industry. However, the technical advantages of composite patternless casting in terms of energy saving and emission reduction have not been fully studied. To address this issue, this paper combines the composite patternless casting with the modular division method, and proposes a influence modelling and analysis method for carbon emissions and carbon efficiency ratio based on the process characteristics stage. The model and method are applied to the patternless casting process of a cylinder block. And the modular division schemes of the mould were proposed. The results show that through different modular division schemes, carbon emissions can be effectively reduced by 8.39%, the carbon efficiency ratio can be increased by up to 30%. This method is helpful to describe the carbon emission influence of the patternless casting forming process, and analyse the energy saving and emission reduction potential and carbon efficiency of the process.

Compact Word-Serial Modular Multiplier Accelerator Structure for Cryptographic Processors in IoT Edge Nodes with Limited Resources

IoT is extensively used in many infrastructure applications, including telehealth, smart homes, smart grids, and smart cities. However, IoT has the weakest link in system security since it often has low processing and power resources. It is important to implement the necessary cryptographic primitives in these devices using extremely efficient finite field hardware structures. Modular multiplication is the core of cryptographic operators. Therefore, we present, in this work, a word-serial modular multiplier accelerator structure that provides the system designer with the ability to manage areas, delays, and energy consumption through selecting the appropriate embedded processor word size l. The modularity and regularity of the suggested multiplier structure makes it more suitable for implementation in ASIC technology. The ASIC implementation results indicates that the offered multiplier structure achieves area reduction compared to the competitive existing multiplier structures that vary from 76.2% to 98.5% for l=8, from 73.1% to 98.1% for l=16, and from 82.9% to 98.3% for l=32. Moreover, the energy reduction varies from 61.2% to 98.8% for l=8, from 67.7% to 98.3% for l=16, and from 76.1% to 98.8% for l=32. These results indicate that the proposed modular multiplier structure significantly outperforms the competitive ones, in terms of area and consumed energy, making it more suitable for utilization in resource-constrained IoT edge devices.

AMBTC-based secret image sharing by simple modular arithmetic

A distortionless secret image sharing scheme using finite field GF(PG) (PG is the largest prime less than a given number) is investigated for sharing the absolute moment block truncation coding (AMBTC) images. Two adjusting operations are devised to modify the AMBTC trios (i.e., quantization pixels and bit maps) suitable for GF(PG) sharing. Polynomials under GF(PG) are constructed for encrypting the quantization pixels and bit maps. When sharing the trios under GF(PG), the AMBTC image is perfectly recovered. Moreover, the bit map sharing under GF(PG) can be extended to GF(PS) (PS is the smallest prime larger than a given number). Another scheme using GF(PS) is constituted by combining quantization pixel sharing under GF(PG) and bit map sharing under GF(PS). But the scheme using GF(PS) is not always lossless. Experimental results show that the proposed schemes are effective. Since GF(PG) and GF(PS) are simple modular arithmetic, improved computational efficiency is obtained.

Fast Supersingular Isogeny Diffie–Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier

We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times faster while improving the AT by at least 1.35 times over all SIKE primes. We have also evaluated our implementation on two other FPGAs. The implementation on Artix-7 improves the time and the AT of performing these two steps of SIKE by at least 1.90 and 1.80 times, respectively. On Kintex UltraScale+, these improvement factors are 2.05 and 2.08, respectively. On this device, these two steps take 3.11, 3.52, 4.66, and 6.59 milliseconds on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$p_{434}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$p_{503}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$p_{610}$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$p_{751}$ </tex-math></inline-formula> , respectively.

Efficient Predicate Evaluation Using Randomized Degeneracy Detection

Computational geometry algorithms branch on the signs of predicates. Prior predicate evaluation techniques are slow on degenerate (zero sign) predicates, especially on predicates on algebraic numbers. Degeneracy is common for predicates whose arguments have common antecedents. We present three randomized algorithms for degeneracy detection. The first algorithm uses modular arithmetic to detect degenerate predicates on rational numbers. The second algorithm uses quotient rings to reduce detecting degenerate predicates on algebraic numbers to multiple rational predicates, which can be evaluated deterministically or using the first algorithm. This algorithm is impractical because it is exponential in the number of algebraic numbers, yet it is still much faster than prior work that uses root separation bounds. The third algorithm uses a perturbation to eliminate degenerate algebraic predicates that are not identical to zero and a second perturbation to detect those that are. The first and third algorithms are incorporated into an exact geometric computation library. By sampling values generated by the algorithms, the library estimates the degeneracy detection failure probability over the lifetime of every calling program. We call this approach statistical degeneracy detection (SDD). Extensive testing shows that predicate evaluation is reliable and fast.

Fast Montgomery Modular Multiplier Using FPGAs

This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the performance of the proposal, a sequential version of the algorithm was also implemented in hardware. Moreover, we compared the parallel implementation with a software version and with five contributions from the literature. This way, we found that our proposal improves the performance of all other implementations.

An initial framework for analyzing students’ reasoning with equivalence across mathematical domains

The concept of equivalence is foundational in mathematics and is pervasive in the K-16 curriculum. Though much research has focused on equivalence, nearly all of it is domain-specific, and it is therefore unclear how students’ reasoning about equivalence in one domain might influence their reasoning about it in another, if at all. This highlights a need for increased theoretical unity and coherence. In this theoretical paper, we propose an initial framework for analyzing students’ reasoning about equivalence across domains. We use the framework to highlight commonalities amongst the ways in which equivalence is interpreted with respect to fractions, K-12 algebra, modular arithmetic, and linear algebra. We demonstrate the framework’s strength as an analytical tool by using it to conduct detailed analyses of student data from already-published studies in combinatorics and abstract algebra. We conclude by suggesting ways in which this framework lays a rich foundation for future research.

High-Radix Design of a Scalable Montgomery Modular Multiplier With Low Latency

The proposed herein is a scalable high-radix (i.e., <inline-formula><tex-math notation="LaTeX">$2^m$</tex-math><alternatives><mml:math><mml:msup><mml:mn>2</mml:mn><mml:mi>m</mml:mi></mml:msup></mml:math><inline-graphic xlink:href="zhang-ieq1-3052999.gif"/></alternatives></inline-formula>) Montgomery Modular (MM) Multiplication circuit replacing the integer multiplications in each iteration of the Montgomery MM algorithm (related to the product of <inline-formula><tex-math notation="LaTeX">$m$</tex-math><alternatives><mml:math><mml:mi>m</mml:mi></mml:math><inline-graphic xlink:href="zhang-ieq2-3052999.gif"/></alternatives></inline-formula> bits of the multiplier and the multiplicand) with carry-save compressions and completely eliminating costly multiplications. Furthermore, the proposed Montgomery MM decomposes the multiplicand itself using a radix of <inline-formula><tex-math notation="LaTeX">$2^w$</tex-math><alternatives><mml:math><mml:msup><mml:mn>2</mml:mn><mml:mi>w</mml:mi></mml:msup></mml:math><inline-graphic xlink:href="zhang-ieq3-3052999.gif"/></alternatives></inline-formula> with <inline-formula><tex-math notation="LaTeX">$w\geq 2m$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>w</mml:mi><mml:mo>&#x2265;</mml:mo><mml:mn>2</mml:mn><mml:mi>m</mml:mi></mml:mrow></mml:math><inline-graphic xlink:href="zhang-ieq4-3052999.gif"/></alternatives></inline-formula>, thereby achieving a scalable design, which can deliver an issue latency of one cycle and a cycle (count) latency of <inline-formula><tex-math notation="LaTeX">$O(N^2/(wmp))$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>O</mml:mi><mml:mo>(</mml:mo><mml:msup><mml:mi>N</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mo>/</mml:mo><mml:mrow><mml:mo>(</mml:mo><mml:mi>w</mml:mi><mml:mi>m</mml:mi><mml:mi>p</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="zhang-ieq5-3052999.gif"/></alternatives></inline-formula> where <inline-formula><tex-math notation="LaTeX">$p$</tex-math><alternatives><mml:math><mml:mi>p</mml:mi></mml:math><inline-graphic xlink:href="zhang-ieq6-3052999.gif"/></alternatives></inline-formula> denotes the number of available processing elements, each of which is designed to complete the above iteration by computing in part the product of <inline-formula><tex-math notation="LaTeX">$w$</tex-math><alternatives><mml:math><mml:mi>w</mml:mi></mml:math><inline-graphic xlink:href="zhang-ieq7-3052999.gif"/></alternatives></inline-formula> bits of the multiplicand and <inline-formula><tex-math notation="LaTeX">$m$</tex-math><alternatives><mml:math><mml:mi>m</mml:mi></mml:math><inline-graphic xlink:href="zhang-ieq8-3052999.gif"/></alternatives></inline-formula> bits of the multiplier. The area complexity of the proposed Montgomery MM is <inline-formula><tex-math notation="LaTeX">$O(wmp)$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>O</mml:mi><mml:mo>(</mml:mo><mml:mi>w</mml:mi><mml:mi>m</mml:mi><mml:mi>p</mml:mi><mml:mo>)</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="zhang-ieq9-3052999.gif"/></alternatives></inline-formula>, and thus, the Area-Latency-Product complexity is <inline-formula><tex-math notation="LaTeX">$O(N^{2})$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>O</mml:mi><mml:mo>(</mml:mo><mml:msup><mml:mi>N</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mo>)</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="zhang-ieq10-3052999.gif"/></alternatives></inline-formula>.

Module-LWE-Based Key Exchange Protocol Using Error Reconciliation Mechanism

Lattice-based key exchange protocols have attracted tremendous attention for its post-quantum security. In this work, we construct a Module-LWE-based key exchange protocol using Peikert’s error reconciliation mechanism. Compared with Kyber.KE, our key exchange protocol reduces the total communication cost by 96-byte, i.e., 3.2% ∼ 6.1%, under the different parameter sets, and without reducing the post-quantum security levels. Moreover, our key exchange protocol slightly reduces the probability of session key agreement failure and the time consumed by modular multiplication of numbers and ring elements by approximately 30%. Thus, the key exchange protocol in this paper is more suitable for the lightweight communication systems.

Modeling an Edge Computing Arithmetic Framework for IoT Environments.

IoT environments are forecasted to grow exponentially in the coming years thanks to the recent advances in both edge computing and artificial intelligence. In this paper, a model of remote computing scheme is presented, where three layers of computing nodes are put in place in order to optimize the computing and forwarding tasks. In this sense, a generic layout has been designed so as to easily achieve communications among the diverse layers by means of simple arithmetic operations, which may result in saving resources in all nodes involved. Traffic forwarding is undertaken by means of forwarding tables within network devices, which need to be searched upon in order to find the proper destination, and that process may be resource-consuming as the number of entries in such tables grow. However, the arithmetic framework proposed may speed up the traffic forwarding decisions as relaying on integer divisions and modular arithmetic, which may result more straightforward. Furthermore, two diverse approaches have been proposed to formally describe such a design by means of coding with Spin/Promela, or otherwise, by using an algebraic approach with Algebra of Communicating Processes (ACP), resulting in a explosion state for the former and a specified and verified model in the latter.

Efficient and Scalable Hardware Implementation of Montgomery Modular Multiplication

Modular multiplication (MM) is an important arithmetic operation in public key cryptography (PKC). In this paper, we present the FPGA implementation of the MM using Montgomery MM (MMM) algorithm. The execution performances of this operation depend on the radix-[Formula: see text] and the operands length. In fact, when increasing the radix-[Formula: see text], the MMM algorithm requires multiplications of digit by operand. On the other hand, when a long modulus is used, the hardware implementation of the MMM needs a large area. Our objective in this work is to realize a scalable architecture able to support any operands length. In order to achieve a best trade-off between computation throughput and hardware resources, our implementation approach is based on the execution of the basic arithmetic operations in serial way. In addition, efficient parallel and pipelined strategies are realized at low-level abstraction for the optimization of the execution time. The implementations results on Virtex-7 circuit show that a 1024-bit MMM runs in 2.09[Formula: see text][Formula: see text]s and consumes 581 slices.

Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design

At present, there are several pieces of research on designing and implementing new cryptographic algorithms that are lightweight and resistant to several, if not major forms of security attacks. However, some algorithms such as the International Data Encryption Algorithm (IDEA), which has been around for some time is yet to record any real threat against its functionality. To ensure its continued usage, current implementations rely on multiphase encryption where it is combined with other algorithms such as ROTation (ROT) and Data Encryption Standard (DES) for maximum security strength. Multiphase encryption implies that there is a tendency for an increase in hardware area and a reduction in overall speed. In such cases, having fast and reduced area algorithms are much desired. This paper, therefore, proposes an efficient hardware implementation of the IDEA cipher that is based on arithmetic modulo multiplication—one of the main computations of the IDEA—on a novel Vedic multiplier architecture. The increase in efficiency of the IDEA crypto architecture and the reduction in resources utilization is achieved through an enhancement of its structural architecture to utilize a fixed set of resources for all eight identical rounds of computation and the use of a proposed fast and lightweight Vedic hardware multiplier. The proposed hardware modification and resulting architecture are designed using the Xilinx ISE and Vivado tools. The architecture is synthesized using Precision Synthesis Tool (PS) and simulated using Modelsim SE 10.6d and ISIM simulation tools. The proposed IDEA cipher is 100% more efficient when designed based on the Vedic multiplier compared to existing designs. The hardware architecture is implemented on Spartan-6-FGG484 Field Programmable Gate Array (FPGA) using Verilog HDL. Verified results show that the proposed Vedic-based IDEA occupied 212 Slices with the Vedic multiplier only occupying 28 Slices out of the total 212. The proposed architecture operates at a maximum frequency of 253.3 MHz.

CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication

In this paper, we introduce a configurable hardware architecture that can be used to generate unified and parametric NTT-based polynomial multipliers that support a wide range of parameters of lattice-based cryptographic schemes proposed for post-quantum cryptography. Both NTT and inverse NTT operations can be performed using the unified butterfly unit of our architecture, which constitutes the core building block in NTT operations. The multitude of this unit plays an essential role in achieving the performance goals of a specific application area or platform. To this end, the architecture takes the size of butterfly units as input and generates an efficient NTT-based polynomial multiplier hardware to achieve the desired throughput and area requirements. More specifically, the proposed hardware architecture provides run-time configurability for the scheme parameters and compile-time configurability for throughput and area requirements. This work presents the first architecture with both run-time and compile-time configurability for NTT-based polynomial multiplication operations to the best of our knowledge. The implementation results indicate that the advanced configurability has a negligible impact on the time and area of the proposed architecture and that its performance is on par with the state-of-the-art implementations in the literature, if not better. The proposed architecture comprises various sub-blocks such as modular multiplier and butterfly units, each of which can be of interest on its own for accelerating lattice-based cryptography. Thus, we provide the design rationale of each sub-block and compare it with those in the literature, including our earlier works in terms of configurability and performance.

Lightweight Secure Integer Comparison

We solve the millionaires problem in the semi-trusted model with homomorphic encryption without using intermediate decryptions. This leads to the computationally least expensive solution with homomorphic encryption so far, with a low bandwidth and very low storage complexity. The number of modular multiplications needed is less than the number of modular multiplications needed for one Pallier encryption. The output of the protocol can be either publicly known, encrypted, or secret-shared. The private input of the first player is computationally secure towards the second player, and the private input of the second player is even unconditionally secure towards the first player. We also introduce an efficient client-server solution for the millionaires problem with similar security properties.

Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases

This paper presents a new architecture to perform modular multiplication using Montgomery multiplication in Residue Number System (RNS). Two new balanced four-moduli RNS bases are selected, and the process of RNS Montgomery multiplication, including the required RNS to RNS conversions, is designed and implemented. Field-programmable gate array (FPGA) implementation using the adder-based residue/binary to binary/residue converters and ROM-free in the pipelined architecture has achieved better performance compared to the state-of-the-art works in literature.

Improved Modular Division Implementation with the Akushsky Core Function

The residue number system (RNS) is widely used in different areas due to the efficiency of modular addition and multiplication operations. However, non-modular operations, such as sign and division operations, are computationally complex. A fractional representation based on the Chinese remainder theorem is widely used. In some cases, this method gives an incorrect result associated with round-off calculation errors. In this paper, we optimize the division operation in RNS using the Akushsky core function without critical cores. We show that the proposed method reduces the size of the operands by half and does not require additional restrictions on the divisor as in the division algorithm in RNS based on the approximate method.

Arithmetic Framework to Optimize Packet Forwarding among End Devices in Generic Edge Computing Environments.

Multi-access edge computing implementations are ever increasing in both the number of deployments and the areas of application. In this context, the easiness in the operations of packet forwarding between two end devices being part of a particular edge computing infrastructure may allow for a more efficient performance. In this paper, an arithmetic framework based in a layered approach has been proposed in order to optimize the packet forwarding actions, such as routing and switching, in generic edge computing environments by taking advantage of the properties of integer division and modular arithmetic, thus simplifying the search of the proper next hop to reach the desired destination into simple arithmetic operations, as opposed to having to look into the routing or switching tables. In this sense, the different type of communications within a generic edge computing environment are first studied, and afterwards, three diverse case scenarios have been described according to the arithmetic framework proposed, where all of them have been further verified by using arithmetic means with the help of applying theorems, as well as algebraic means, with the help of searching for behavioral equivalences.

Efficient Floating Point Arithmetic for Quantum Computers

One of the major promises of quantum computing is the realization of SIMD (single instruction - multiple data) operations using the phenomenon of superposition. Since the dimension of the state space grows exponentially with the number of qubits, we can easily reach situations where we pay less than a single quantum gate per data point for data-processing instructions which would be rather expensive in classical computing. Formulating such instructions in terms of quantum gates, however, still remains a challenging task. Laying out the foundational functions for more advanced data-processing is therefore a subject of paramount importance for advancing the realm of quantum computing. In this paper, we introduce the formalism of encoding so called-semi-boolean polynomials. As it turns out, arithmetic Z/2^<i>n</i>Z ring operations can be formulated as semi-boolean polynomial evaluations, which allows convenient generation of unsigned integer arithmetic quantum circuits. For arithmetic evaluations, the resulting algorithm has been known as Fourier-arithmetic. We extend this type of algorithm with additional features, such as ancilla-free in-place multiplication and integer coefficient polynomial evaluation. Furthermore, we introduce a tailormade method for encoding signed integers succeeded by an encoding for arbitrary floating-point numbers. This representation of floating-point numbers and their processing can be applied to any quantum algorithm that performs unsigned modular integer arithmetic. We discuss some further performance enhancements of the semi boolean polynomial encoder and finally supply a complexity estimation. The application of our methods to a 32-bit unsigned integer multiplication demonstrated a 90% circuit depth reduction compared to carry-ripple approaches.

A summary of feature selection techniques for gene chip in bioinformatics based on RSA algorithm

With the implementation of the human genome project, computational intelligence has been widely used in computational biology and bioinformatics. The purpose of this study is to study the feature selection technique of gene chip in bioinformatics. In this paper, a binary key scanning method is used to decompose the model power algorithm into a series of modular multiplication operations. At the same time, the combination of genetic algorithm and RSA algorithm is used to select the feature of high dimensional space. The problem of sample classification of two categories is solved. The method is used for the design of the sequencing chip and gene expression chip. The final research shows that the RSA algorithm is applied to the technology of gene chip selection, and a high-density gene chip design software system and experimental result analysis system can be developed.