Modular Multiplication Architecture Research Articles

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion

Modular multiplication is a key operation in RSA cryptosystems. Modular multipliers can be realized using Montgomery algorithm. Montgomery algorithm employing carry save adders makes modular multiplication suitable and efficient. Montgomery modular multiplication can be carried out in two ways. All the operands are kept in carry save form in one of the ways. The input and output are kept in binary form, and intermediate operands are kept in carry save form in the other way which requires an efficient format converter. This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method. Format conversion is carried out through a format conversion unit which consists of a carry look-ahead unit and multiplexer unit. In addition, this multiplier merges two iterations, which reduces the number of clock cycles significantly. Merger of iteration requires integer multiples of inputs which is computed using the same format converter. Critical path delay of the multiplier is minimized by multiplying one of the inputs by four which simplifies necessary intermediate calculations. The total time required for one complete multiplication is significantly minimized due to reduction in required number of clock cycles with optimum critical path delay. Experimental results show that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.

Secure and Dependable NoC-Connected Systems on an FPGA Chip

The growing reliance on intellectual properties exposes systems on chip (SoCs) to many security vulnerabilities and is raising more and more concerns. At the same time, with the quick increase in chip density and deep scaling of feature size, current billion-transistor chip designs introduce more challenges to manufacturing fault-free chips. In this paper, we propose an integrated run-time solution for both security and fault tolerance of field-programmable gate arrays (FPGA)-based SoCs through digital signatures, live monitoring, adaptive routing, and partial reconfiguration supported by an in-house-developed network on chip, X-Network. Our X-Network reduces the ratio of required routers versus processing elements with better performance, and more importantly, offers more flexibility than conventional networks to facilitate fault tolerance and security designs. A multiplexed Montgomery modular multiplication architecture is used to increase the speed of the Rivest-Shamir-Adleman algorithm. The design has been implemented and tested on a Xilinx Virtex-6 FPGA development board. Experimental results show that even if up to 20% of the links in the network are faulty, our reconfigurable architecture and algorithm manage to route packets around such faults, and deliver them to their destinations in a relatively low latency. Unlike conventional fault-tolerant methods that usually require resource redundancy, our design does not incur significant area or speed degradation. The resource overhead for both security and fault-tolerant features is around 10% more lookup tables.

Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture

Secure communication is a challenging issue in modern industries and critical infrastructures. The core technology used for securing the communication is cryptography. Modular multiplication is an important operation in cryptosystems. This paper investigates a novel modular multiplication algorithm and architecture. In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. The proposed architecture is implemented on Xilinx Virtex 5 FPGA. The complexity analysis results and FPGA implementation results show that the proposed modular multiplication algorithm and architecture provide improvement on the total computation time and area×time complexity compared to other modified modular multiplication algorithms and architectures. Keyword: Security, modular multiplication architecture, FPGA, parallel computation, compact SD

Scalable GF( p ) Montgomery multiplier based on a digit–digit computation approach

This study presents a scalable hardware architecture for modular multiplication in prime fields GF( p ). A novel iterative digit-digit Montgomery multiplication (IDDMM) algorithm is proposed and two hardware architectures that compute that algorithm are described. The input operands (multiplicand, multiplier and modulus) are represented using as radix β = 2 k . Multiplication over GF( p ) is possible using almost the same hardware since the complexity of multiplier's kernel module depends mainly on k and not on p . The novel hardware architectures of GF( p ) multipliers were evaluated on three Xilinx FPGA families. Design trade-offs were analysed considering different operand sizes commonly used in cryptography and different digits sizes. The proposed designs for IDDMM are well suited to be implemented in modern FPGAs, making use of available dedicated multipliers and memory blocks reducing drastically the FPGA's standard logic while keeping an acceptable performance compared with other implementation approaches. From the Virtex5 implementation, the proposed MM multiplier reaches a throughput of 242 Mbps using only 219 FPGA slices and achieving a 1024-bit modular multiplication in 4.21μs. This is 26 times less area resources than similar related works in the literature with an improved efficiency of 7x.

High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan–Multibit-Shift Technique

Modular exponentiation with a large modulus and exponent is a fundamental operation in many public-key cryptosystems. This operation is usually accomplished by repeating modular multiplications. Montgomery modular multiplication has been widely used to relax the quotient determination. The carry-save adder has been employed to reduce the critical path. This paper presents and evaluates a new and efficient Montgomery modular multiplication architecture based on a new digit serial computation. The proposed architecture relaxes the high-radix partial multiplication to a binary multiplication. It also performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles. Moreover, the right-to-left and left-to-right modular exponentiation architectures have been modified to use the proposed modular multiplication architecture as its structural unit. We provide the implementation results on a Xilinx Virtex 5 FPGA demonstrating that the total computation time and throughput rate of the proposed architectures outperform most results so far in the literatures.

New systolic modular multiplication architecture for efficient Montgomery multiplication

New systolic modular multiplication architecture for efficient Montgomery multiplication

Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement

Montgomery modular multiplication is widely used in public-key cryptosystems. This work shows how to relax the data dependency in conventional word-based algorithms to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, we then proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost 1/(w - 1) times that of conventional scalable architectures, where w denotes word size. The proposed one also retains a latency of exactly one cycle between the operations of the same words in two consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. Compared to the design in the related work, experimental results demonstrate that the proposed one achieves an almost 54 percent reduction in power consumption with no degradation in throughput. The reduced number of memory access not only leads to lower power consumption, but also facilitates the design of scalable architectures for any precision of operands.

On the generalisation of special moduli for faster interleaved montgomery modular multiplication

In this study, the authors give a generalisation of special moduli for faster interleaved Montgomery modular multiplication algorithm with simplified pre-computational phase for GF(pn ), where p ≥ 2 is a prime number and n is a positive integer. The authors propose different sets of moduli that can be used in elliptic curve crytographic applications and pairing-based cryptography. Moreover, this method also leads to efficient implementations for the elliptic curve parameters given in standards. It is shown that one can obtain efficient Montgomery modular multiplication architecture in view of the number of AND gates and XOR gates by choosing proposed sets of moduli. The authors eliminate final substraction step with proposed sets of moduli. These methods are easy to implement for hardware.

Architecture Optimizations for the RSA Public Key Cryptosystem: A Tutorial

The Rivest Shamir Adleman (RSA) cryptosystem, named after its creators, is one of the most popular public key cryptosystems. The RSA cryptosystem has been utilized for e-commerce, various forms of authentication, and virtual private networks. The importance of high security and faster implementations paved the way for RSA crypto-accelerators, hardware implementations of the RSA algorithm. This work consists of describing various approaches to implementing RSA crypto-accelerators based on the “textbook” version of the RSA cryptosystem and comparing their area requirements. Many of the techniques described here have applications elsewhere such as in digital signal processing and error correcting codes. This paper presents the four fundamental architectures: the bit- serial squaring architecture, two bit-serial systolic array modular multiplication architectures, and the interleaved modular multiplication architecture.

Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare thetime×areaefficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23 ms, and the multiplexed architecture executes the same operation in 4.36 ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.

Selected Papers from the Southern Programmable Logic Conference (SPL2010)

This is the third special issue published in this journal with selected contributions from the VI Southern Conference on Programmable Logic (SPL, www.splconf.org). SPL is one of the first-class conferences on programmable logic around the world. Started in 2005, SPL has since 2007 the technical cosponsorship of the IEEE Circuits and Systems Society (CAS). The conference has been always organized in the south hemisphere. The selection of papers presented in this special issue is coming from the last 6th edition, held in Ipojuca, Brazil, from March 24 to 26, 2010. This issue is focused on speech and video acceleration applications. The first paper by P. Eh Kan et al., “FPGA implementation for GMM-based speaker identification” in the area of biometric-based speaker identification, describes the hardware implementation for classification of a text-independent (Gaussian mixture model) GMMbased speaker identification system. Authors show that the proposed hardware implementation allows simultaneous identification processing for a large number of voice streams in real time. In “FPGA implementation of a pipelined Gaussian calculation for HMM-based large-vocabulary speech recognition,” R. Veitch et al. present several alternatives for a Gaussian core as part of a larger speech recognition system. These cores are developed as an embedded peripheral and as a scalable, parallel hardware accelerator. Next, in “A high throughput hardware architecture for the H.264/AVC half-pixel motion estimation targeting high definition videos,” M. M. Correa et al. present a highperformance hardware implementation for the H.264/AVC half-pixel motion estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840 × 2048) in real time (30 frames per second). E. C. Pedrino et al. in the area of computer vision presented “A genetic programming approach to reconfigure a morphological image processing architecture.” They report the development of a reconfigurable architecture using logical, arithmetic, and morphological instructions generated automatically by a genetic programming approach. Related to cryptographic algorithms, G. Perin et al., in “Montgomery modular multiplication on reconfigurable hardware: systolic versus multiplexed implementation,” develop two Montgomery modular multiplication architectures: a systolic and a multiplexed circuit with competitive results. Finally, A. G. Silva-Filho et al. presented an advanced EDA tool in the paper “An ESL approach for energy consumption analysis of cache memories in SoC platforms” in the area of design space exploration. They propose an electronicsystem-level (ESL) approach for system modeling and cache energy consumption analysis of SoCs.

An efficient CSA architecture for montgomery modular multiplication

Montgomery multipliers of carry save adder (CSA) architecture require a full addition to convert the carry save representation of the result into a conventional form. In this paper, we reuse the CSA architecture to perform the result format conversion, which leads to small area and fast speed. The results of implementation on FPGAs show that the new Montgomery multiplier is about 113.4 Mbit/s for 1024-bit operands at a clock of 114.2 MHz.

시스톨릭 어레이 구조를 갖는 효율적인 n-비트 Radix-4 모듈러 곱셈기 구조

본 논문에서는 Montgomery 알고리즘을 기반으로 시스톨릭 어레이 구조를 이용한 효율적인 Radix-4 모듈러 곱셈기 구조를 제안한다. 제안된 알고리즘을 이용하여 모듈러 곱셈을 위한 반복의 수가 감소되었으며, 따라서 n-비트의 모듈러 곱셈을 수행하기 위하여 (3/2)n+2 클럭이 소요된다. 그러나 하드웨어의 이용도를 감안할 때 두 개의 곱셈에 대한 중첩(interleaving) 연산이 가능하며, 가장 빠른 시기에 새로운 곱셈을 시작한다면 하나의 모듈러 곱셈을 수행하기 위하여 평균 n/2 클럭이 필요하다. 제안된 구조는 시스톨릭 어레이 구조의 잇점으로 규칙성과 확장성을 갖기 때문에 효율적인 VLSI 구조로 설계하기가 용이하다. 기존의 다른 구조들과 비교하여 볼 때 제안된 구조는 상대적으로 적은 하드웨어들을 사용하여 높은 수행 속도를 보여주었다. In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

A scalable architecture for modular multiplication based on montgomery's algorithm

This paper presents a scalable architecture for the computation of modular multiplication, based on the Montgomery multiplication (MM) algorithm. A word-based version of MM is presented and used to explain the main concepts in the hardware design. The proposed multiplier is able to work with any precision of the input operands, limited only by memory or control constraints. Its architecture gives enough freedom to select the word size and the degree of parallelism to be used, according to the available area and/or desired performance. Design trade offs are analyzed in order to identify adequate hardware configurations for a given area or bandwidth requirement.

Performance-scalable array architectures for modular multiplication

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. The increasing popularity of Internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.

Partitioned systolic architecture for modular multiplication in [formula omitted

This letter proposes a partitioned systolic array for MSB-first approach multiplication in GF(2 m) . When compared to the related multiplier presented by Wang, the proposed systolic array requires a significantly smaller number of basic cells. It requires only m/2 basic cells and exhibits the same latency when it has two bands.

Optimised bit serial modular multiplier for implementation on field programmable gate arrays

A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the re-programmability of the FPGA, such that a longer bit length can be implemented on the same FPGA.