Modified Euclidean Algorithm Research Articles

Main melody extraction from polyphonic music based on modified Euclidean algorithm

Extracting main melody from polyphonic music is one of the most appealing and challenging tasks in music information retrieval (MIR). In this paper, a new melody extraction method based on a modified Euclidean algorithm (MEA) is proposed. Firstly, the instantaneous frequency is adopted to gain better frequency discrimination, and the frame-wise pitch candidates are estimated based on the modified Euclidean algorithm. Next, the candidate trajectories are formed using these potential candidates, and padded by the candidate one octave above or below if there is a gap at some isolated frames. Finally, the melodic contours are extracted using the melody smoothness and salience principle. The proposed modified Euclidean algorithm can deal with diverse coprime harmonic combinations, and work well at low computational cost and memory requirement. The experimental results show that the proposed method can extract main melody extraction effectively with few pitch candidates.

Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems

A low-complexity Reed-Solomon (RS) decoder design based on the modified Euclidean (ME) algorithm proposed by Truong is presented in this paper. Low complexity is achieved by reformulating Truong's ME algorithm using the proposed polynomial manipulation scheme so that a more compact polynomial representation can be derived. Together with the developed folding scheme and simplified boundary cell, the resulting design effectively reduces the hardware complexity while meeting the throughput requirements of optical communication systems. Experimental results demonstrate that the developed RS(255, 239) decoder, implemented in the TSMC 0.18µm process, can operate at up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 11,759. Compared to related works, the proposed decoder has the lowest area requirement and the smallest area-time complexity.

High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255, 239) decoder design, implemented using the TSMC 0.18µm process, can reach a throughput rate of 3Gbps at an operating frequency of 375MHz and with a total gate count of 27, 271.

An area-efficient very large scale integration architecture for modified Euclidean algorithm with dynamic storage technique

A Modified Euclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties, an area-efficient very large scale integration (VLSI) architecture with dynamic storage technique is proposed to perform the ME algorithm. The dynamic storage technique is used to avoid data exchange and save hardware resources. The proposed architecture with dynamic storage technique can reduce 50% computation hardware area and about 30% memory hardware area. VLSI implementation results of different RS codes show that the proposed architecture is significantly area-efficient, especially for RS codes with long code lengths.

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders

This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-μm CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.

An efficient recursive cell architecture of modified euclid's algorithm for decoding reed-solomon codes

For decoding Reed-Solomon (RS) codes, the Belekamp-Messay algorithm, Euclid's algorithm and modified Euclid's algorithm (MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The proposed architecture uses about 25% less clock cycles required in the MEA operation than the conventional scheme. In addition, the number of recursive MEA cells can be reduced when the number of clock cycles spent in the MEA operation is larger than code word length n. Thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circuitry for (128, 124) RS code has been described and the MEA operation is verified through VHDL modeling.

Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed–Solomon decoder

A novel pipelined recursive modified Euclidean (ME) algorithm block for the low-complexity, high-speed Reed–Solomon (RS) decoder is presented. The deeply pipelined recursive structure enables implementation of a significantly low-complexity ME algorithm block with much improved clock frequency. The low-complexity, high-speed RS decoder using the pipelined recursive ME algorithm block has been implemented in 0.13 µm CMOS technology with a supply voltage of 1.1 V. The results show that it has significantly low hardware complexity and a high data processing rate of 6.16 Gbit/s.

Architecture for decoding adaptive Reed-Solomon codes with variable block length

An adaptive Reed-Solomon (RS) decoder is designed, which can decode RS codes of any block length n as well as any message length k. This unique feature is favorable for a shortened RS code, since it eliminates the need to insert zeros before decoding the code. Furthermore, the value of error-correcting capability t can be changed at every codeword block. The decoder permits 4-step pipelined processing based on the modified Euclid's algorithm (MEA). Each step has a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for varying values of t. The operating length of the shift registers shortened by one can be adjusted to be varied according to the different values of t. To maintain the throughput rate with less circuitry, the MEA block uses both the multiplexing and recursive technique and the overclocking technique. The adaptive RS decoder over GF(2/sup 8/) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in a FPGA chip.

Modified Euclidean algorithm block for high-speed Reed-Solomon decoder

A new modified Euclidean (ME) algorithm block for the high-speed Reed-Solomon (RS) decoder is presented. The RS decoder using the ME algorithm has been implemented with standard 0.16 µm CMOS cell technology with a supply voltage of 1.5 V. The results show that it operates at a clock frequency of 300 MHz and has a data processing rate of 2.4 Gbit/s.