Modern Multi Research Articles

RabbitFX: Efficient Framework for FASTA/Q File Parsing on Modern Multi-Core Platforms.

The continuous growth of generated sequencing data leads to the development of a variety of associated bioinformatics tools. However, many of them are not able to fully exploit the resources of modern multi-core systems since they are bottlenecked by parsing files leading to slow execution times. This motivates the design of an efficient method for parsing sequencing data that can exploit the power of modern hardware, especially for modern CPUs with fast storage devices. We have developed RabbitFX, a fast, efficient, and easy-to-use framework for processing biological sequencing data on modern multi-core platforms. It can efficiently read FASTA and FASTQ files by combining a lightweight parsing method by means of an optimized formatting implementation. Furthermore, we provide user-friendly and modularized C++ APIs that can be easily integrated into applications in order to increase their file parsing speed. As proof-of-concept, we have integrated RabbitFX into three I/O-intensive applications: fastp, Ktrim, and Mash. Our evaluation shows that the inclusion of RabbitFX leads to speedups of at least 11.6 (6.6), 2.4 (2.4), and 3.7 (3.2) compared to the original versions on plain (gzip-compressed) files, respectively. These case studies demonstrate that RabbitFX can be easily integrated into a variety of NGS analysis tools to significantly reduce associated runtimes. It is open source software available at https://github.com/RabbitBio/RabbitFX.

Use of Modern Multi- and Hyperspectral Space Images for Mapping Hydrothermal Alteration and Lithological Units in the Arctic

Use of Modern Multi- and Hyperspectral Space Images for Mapping Hydrothermal Alteration and Lithological Units in the Arctic

An efficient medical image encryption scheme for (WBAN) based on adaptive DNA and modern multi chaotic map

A Wireless Body Area Network (WBAN) is a network of wireless sensor nodes that can be installed inside or outside of the human body. This network is crucial in medical problems. Due to storage, battery power, and computational resource limitations, the security of medical information such as medical photographs or other information is a major concern in (WBAN). This work proposes an image encryption approach that addresses these constraints by utilizing adaptive DNA code bases and a new multi chaotic map architecture. DNA coding is used to enhances computing efficiency and gives great data transfer capabilities and the new multi chaotic map was formed by Combining Henon, Gaussian and Logistic map (HGL) To generate more chaotic pseudo-random sequences. Numerous analyses were conducted to test the proposed scheme, such as brute force, statistical, differential assaults and noise added analysis. Results indicated that this scheme has a strong level of security.

Mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies

With growing numbers of cores, the memory subsystem of manycore architectures increases in complexity. Many modern multicores are designed in a hierarchical fashion, with multiple clusters of processing elements. However, most algorithms for design-space exploration of resource allocation in multicores do not consider these complex topologies, which results in poor scaling, or worse, non-functioning algorithms. In this paper we present mpsym, a C++ library designed to alleviate this problem in an algorithm-agnostic fashion. Using methods from computational group theory, we present domain-specific algorithms to improve design-space exploration in hierarchical architecture topologies. We evaluate mpsym on multiple designspace exploration algorithms from literature. Without modifying the algorithm, our methods improve the execution time by a factor up to 8:6× on the E3S benchmark suite for complex, clustered architecture topologies. Similarly, by pruning the design space, our methods consistently improve the result of the exploration. In particular, the results from a simulated annealing heuristic on the Kalray MPPA3 Coolidge topology are over 30× better on average, while requiring less time to explore.

Towards Digital Twins of Multimodal Supply Chains

Both modern multi- and intermodal supply chains pose a significant challenge to control and maintain while offering numerous optimization potential. Digital Twins have been proposed to improve supply chains. However, as of today, they are only used for certain parts of the entire supply chain. This paper presents an initial framework for a holistic Digital Supply Chain Twin (DSCT) capable of including an entire multimodal supply chain. Such a DSCT promises to enable several improvements all across the supply chain while also be capable of simulating and evaluate several different scenarios for the supply chain. Therefore, the DSCT will not only be able to optimize multi- and intermodal supply chains but also makes them potentially more robust by identifying possible issues early on. This paper discusses the major requirements that such a DSCT must fulfil to be useful and how several information technologies that matured in recent years or are about the mature are the key enablers to fulfil these requirements. Finally, a suggested high-level architecture for such a DSCT is presented as a first step towards the realization of a DSCT, as presented in this work

A Comparative Study of Techniques for Energy Predictive Modeling Using Performance Monitoring Counters on Modern Multicore CPUs

Accurate and reliable measurement of energy consumption is essential to energy optimization at an application level. Energy predictive modelling using performance monitoring counters (PMCs) emerged as a promising approach, one of the main drivers being its capacity to provide fine-grained component-level breakdown of energy consumption. In this work, we compare two types of energy predictive models constructed from the same set of experimental data and at two levels, platform and application. The first type contains linear regression (LR) models employing PMCs selected using a theoretical model of energy of computing. The second type contains sophisticated statistical learning models, random forest (RF) and neural network (NN), that are based on PMCs selected using correlation and principal component analysis. Our experimental results performed on two modern Intel multicore processors using a diverse set of applications and a wide range of application configurations, show that the average proportional prediction accuracy of platform-level LR models is 5.09× and 4.37× times better than the platform-level RF and NN models. We also present an experimental methodology to select a reliable subset of four PMCs for constructing accurate application-specific online models. Using the methodology, we demonstrate that LR models perform 1.57× and 1.74× times better than RF and NN models. The consistent accuracy of LR models stress the importance of taking into account domain-specific knowledge for model variable selection, in this case, the physical significance of the PMCs originating from the conservation of energy of computing. The results also endorse the guidelines of the theory of energy of computing, which states that any non-linear energy model (in this case, the RF and NN models) employing PMCs only, will be inconsistent and hence inherently inaccurate.

EVALUATION OF THE MASTICATORY PRESSURE VALUE IN HYBRID DENTURES OVER IMPLANTS IN MANDIBULA

In the clinical practice due to various factors we face with patients who have very few teeth left without prospective in the lower jaw. Due to reduced load capacity, they are loosening and soon are completely lost. Prosthodontics is a real magic that has great potential for a unique implant - prosthetic rehabilitation. The goal is to preserve the alveolar ridge and slow down its resorption. In the modern world trends, the conventional dentures are replaced by therapeutic methods and superstructures as modern prosthetic therapy for this problem. As an example of these restorations that are practically applied, we present multi unit system dentures with a single hybrid prosthesis. It is a conditionally mobile suprastructure fixed with screws on 4 implants. The combination of oral surgery with the placement of 4 implants and the hybrid prosthetic superstructure over them is known by a popular short name "all on four". There are many discussions and writings about this multidisciplinary concept in the professional world. Over the 4 implants, immediately is placed suprastructure with a maximum number of 12 teeth. The prosthetic construction circularly covers the entire toothless ridge. Bilaterally, the chewing center is mesialized in the area of the second premolar and first molar. The applied technique is a practical modern multi - combination for immediate rehabilitation and rapid restoration of the chewing function. The data obtained from the subjects with intact dentition indicate a difference in the development of the bite force in the chewing center. Significantly higher values were observed in subjects with a masseteric type of mastication with significant differences in the bite force in the molar region. Functional efficiency was significantly lower in subjects with total tooth loss with classic total dentures. This result is due to the gingival distribution of the load only to the masticatory gingiva and the alveolar ridge. The value of the bite strength in subjects with partial dentures with Kennedy I class of toothlessness according to the registration the performance in the chewing center is higher. There is a combination in the transmission of the pressure, some gingivally, some accept the remaining teeth. The functional efficiency is higher in hybrid denture subjects. The hybrid denture externally resembles a classical one, but unlike it, it is screwed in its base, fixed with nuts on the implants. It is retained exclusively on a minimum of 4 implants placed in the alveolar ridge, which later integrate with the bone during the chewing function. There is minimal mild tangential contact between it and the soft tissues of the alveolar ridge. It has the practical ability to be removed - unscrews for various needs such as perimplantitis treatment, additional plaque hygiene or any other adjustments and polishes. It is often used as immediate prosthetic therapy in patients who are in the transitional phase from partial - subtotal to total toothlessness. Namely, it is preventively applied to slow down the further atrophy of the supporting tissues and the resorption of the alveolar ridge.

Seismic Effect on Multi Storey Building with Different Positioning Of Floating Column

Modern multi storied buildings are being constructed with floating column at the ground floor to meet the requirements of parking or other aesthetic or utility value. Masonry buildings have proved to be most vulnerable when earthquakes strike in any part of the world. The damage caused by the earthquake cannot be eliminated but it could be mitigated by taking extra precaution. Floating columns can be constructed at any level or storey, at any point in the construction area. Seismic analysis is a major tool in earthquake engineering; this is used to understand the response of buildings due to seismic excitations in a simpler manner. Response Spectrum Analysis was used. Assumptions were made to study the seismic effect on different position of floating column for a six storied RC framed building.

Maximizing Performance under a Power Constraint on Modern Multicore Systems

Energy efficiency and energy-proportional computing have become a central focus in modern supercomputers. These supercomputers should provide high throughput per unit of power to be sustainable in terms of operating cost and failure rates. In this paper, a power-bounded strategy is proposed that maximizes parallel application performance under a given power constraint. The strategy dynamically allocates power to core, uncore, and memory power domains within a node to maximize performance under a given power budget. Experiments on a 20-core Haswell-EP platform for a real-world parallel application GAMESS demonstrate that the proposed strategy delivers performance within 4% of the best possible performance for as much as 25% reduction in the minimum power budget required for maximum performance.

NUMA-Caffe

Convolution Neural Networks (CNNs), a special subcategory of Deep Learning Neural Networks (DNNs), have become increasingly popular in industry and academia for their powerful capability in pattern classification, image processing, and speech recognition. Recently, they have been widely adopted in High Performance Computing (HPC) environments for solving complex problems related to modeling, runtime prediction, and big data analysis. Current state-of-the-art designs for DNNs on modern multi- and many-core CPU architectures, such as variants of Caffe, have reported promising performance in speedup and scalability, comparable with the GPU implementations. However, modern CPU architectures employ Non-Uniform Memory Access (NUMA) technique to integrate multiple sockets, which incurs unique challenges for designing highly efficient CNN frameworks. Without a careful design, DNN frameworks can easily suffer from long memory latency due to a large number of memory accesses to remote NUMA domains, resulting in poor scalability. To address this challenge, we propose NUMA-aware multi-solver-based CNN design, named NUMA-Caffe , for accelerating deep learning neural networks on multi- and many-core CPU architectures. NUMA-Caffe is independent of DNN topology, does not impact network convergence rates, and provides superior scalability to the existing Caffe variants. Through a thorough empirical study on four contemporary NUMA-based multi- and many-core architectures, our experimental results demonstrate that NUMA-Caffe significantly outperforms the state-of-the-art Caffe designs in terms of both throughput and scalability.

ClMF: A fine-grained and portable alternating least squares algorithm for parallel matrix factorization

Alternating least squares (ALS) has been proved to be an effective solver for matrix factorization in recommender systems. To speed up factorizing performance, various parallel ALS solvers have been proposed to leverage modern multi-cores and many-cores. Existing implementations are limited in either speed or portability. In this paper, we present an efficient and portable ALS solver (clMF) for recommender systems. On one hand, we diagnose the baseline implementation and observe that it lacks of the awareness of the hierarchical thread organization on modern hardware. To achieve high performance, we apply the thread batching technique, the fine-grained tiling technique and three architecture-specific optimizations. On the other hand, we implement the ALS solver in OpenCL so that it can run on various platforms (CPUs, GPUs and MICs). Based on the architectural specifics, we select a suitable code variant for each platform to efficiently map it to the underlying hardware. The experimental results show that our implementation performs 2.8×–15.7× faster on an Intel 16-core CPU, 23.9×–87.9× faster on an NVIDIA K20C GPU and 34.6×–97.1× faster on an AMD Fury X GPU than the baseline implementation. On the K20C GPU, our implementation also outperforms cuMF over different latent features ranging from 10 to 100 with various real-world recommendation datasets.

Applications of Ear Decomposition to Efficient Heterogeneous Algorithms for Shortest Path/Cycle Problems

Graph algorithms play an important role in several fields of sciences and engineering. Prominent among them are the All-Pairs-Shortest-Paths ( APSP ) and related problems. Indeed there are several efficient implementations for such problems on a variety of modern multi- and many-core architectures. It can be noticed that for several graph problems, parallelism offers only a limited success as current parallel architectures have severe short-comings when deployed for most graph algorithms. At the same time, some of these graphs exhibit clear structural properties due to their sparsity. This calls for particular solution strategies aimed at scalable processing of large, sparse graphs on modern parallel architectures. In this paper, we study the applicability of an ear decomposition of graphs to problems such as all-pairs-shortest-paths and minimum cost cycle basis. Through experimentation, we show that the resulting solutions are scalable in terms of both memory usage and also their speedup over best known current implementations. We believe that our techniques have the potential to be relevant for designing scalable solutions for other computations on large sparse graphs.

Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores

To foster the energy-efficiency in current and future multi-core processors, the benefits and trade-offs of a large set of optimization solutions must be evaluated. For this purpose, it is often crucial to consider how key micro-architecture aspects, such as accessing different memory levels and functional units, affect the attainable power and energy consumption. To ease this process, we propose a set of insightful cache-aware models to characterize the upper-bounds for power, energy and energy-efficiency of modern multi-cores in three different domains of the processor chip: cores, uncore and package. The practical importance of the proposed models is illustrated when optimizing matrix multiplication and deriving a set of power envelopes and energy-efficiency ranges of the micro-architecture for different operating frequencies. The proposed models are experimentally validated on a computing platform with a quad-core Intel 3770K processor by using hardware counters, on-chip power monitoring facilities and assembly micro-benchmarks.

A Software Cache Partitioning System for Hash-Based Caches

Contention on the shared Last-Level Cache (LLC) can have a fundamental negative impact on the performance of applications executed on modern multicores. An interesting software approach to address LLC contention issues is based on page coloring , which is a software technique that attempts to achieve performance isolation by partitioning a shared cache through careful memory management. The key assumption of traditional page coloring is that the cache is physically addressed. However, recent multicore architectures (e.g., Intel Sandy Bridge and later) switched from a physical addressing scheme to a more complex scheme that involves a hash function. Traditional page coloring is ineffective on these recent architectures. In this article, we extend page coloring to work on these recent architectures by proposing a mechanism able to handle their hash-based LLC addressing scheme. Just as for traditional page coloring, the goal of this new mechanism is to deliver performance isolation by avoiding contention on the LLC, thus enabling predictable performance. We implement this mechanism in the Linux kernel, and evaluate it using several benchmarks from the SPEC CPU2006 and PARSEC 3.0 suites. Our results show that our solution is able to deliver performance isolation to concurrently running applications by enforcing partitioning of a Sandy Bridge LLC, which traditional page coloring techniques are not able to handle.

Well-Structured Futures and Cache Locality

In fork-join parallelism, a sequential program is split into a directed acyclic graph of tasks linked by directed dependency edges, and the tasks are executed, possibly in parallel, in an order consistent with their dependencies. A popular and effective way to extend fork-join parallelism is to allow threads to create futures. A thread creates a future to hold the results of a computation, which may or may not be executed in parallel. That result is returned when some thread touches that future, blocking if necessary until the result is ready. Recent research has shown that although futures can, of course, enhance parallelism in a structured way, they can have a deleterious effect on cache locality. In the worst case, futures can incur Ω( PT ∞ + tT ∞ ) deviations, which implies Ω ( CPT ∞ + CtT ∞ ) additional cache misses, where C is the number of cache lines, P is the number of processors, t is the number of touches, and T ∞ is the computation span. Since cache locality has a large impact on software performance on modern multicores, this result is troubling. In this article, we show that if futures are used in a simple, disciplined way, then the situation is much better: if each future is touched only once, either by the thread that created it or by a later descendant of the thread that created it, then parallel executions with work stealing can incur at most O ( CPT 2 ∞ ) additional cache misses—a substantial improvement. This structured use of futures is characteristic of many (but not all) parallel applications.

Accelerating low-fidelity aerodynamic codes on multi- and many-core architectures

Vortex lattice and panel methods belong to a broad family of aerodynamic codes based on potential flow theory. They are used in preliminary aerodynamic studies in early stages of aircraft design where hundreds of thousands candidate configurations are analyzed. In this paper, we describe their efficient implementation on modern multi- and many-core architectures. We show how to bridge the `ninja gap', defined as the performance gap between an unoptimized C/C$$++$$++ code and best optimized CPU code. We port the Vortex Lattice Method to a Graphics Processing Unit using the OpenACC standard. An elegant solution for implementation of data movements for C$$++$$++ classes is also presented.

Can traditional programming bridge the ninja performance gap for parallel computing applications?

Current processor trends of integrating more cores with wider SIMD units, along with a deeper and complex memory hierarchy, have made it increasingly more challenging to extract performance from applications. It is believed by some that traditional approaches to programming do not apply to these modern processors and hence radical new languages must be discovered. In this paper, we question this thinking and offer evidence in support of traditional programming methods and the performance-vs-programming effort effectiveness of common multi-core processors and upcoming many-core architectures in delivering significant speedup, and close-to-optimal performance for commonly used parallel computing workloads. We first quantify the extent of the gap, which is the performance gap between naively written C/C++ code that is parallelism unaware (often serial) and best-optimized code on modern multi-/many-core processors. Using a set of representative throughput computing benchmarks, we show that there is an average Ninja gap of 24X (up to 53X) for a recent 6-core Intel® Core™ i7 X980 Westmere CPU, and that this gap if left unaddressed will inevitably increase. We show how a set of well-known algorithmic changes coupled with advancements in modern compiler technology can bring down the Ninja gap to an average of just 1.3X. These changes typically require low programming effort, as compared to the very high effort in producing Ninja code. We also discuss hardware support for programmability that can reduce the impact of these changes and even further increase programmer productivity. We show equally encouraging results for the upcoming Intel® Many Integrated Core architecture (Intel® MIC) which has more cores and wider SIMD. We thus demonstrate that we can contain the otherwise uncontrolled growth of the Ninja gap and offer a more stable and predictable performance growth over future architectures, offering strong evidence that radical language changes are not required.

Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization

The performance of data-intensive applications, when running on modern multi- and many-core processors, is largely determined by their memory access behavior. Its most important contributors are the frequency and latency of off-chip accesses and the extent to which long-latency memory accesses can be overlapped with useful computation or with each other. In this paper we present two methods to better understand application and microarchitectural interactions. An <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">epoch profile</i> is an intuitive way to understand the relationships between three important characteristics: theon-chip cache size, the size of the reorder window of an out-of-order processor, and the frequency of processor stalls caused by long-latency,off-chip requests (epochs). By relating these three quantities one can more easily understand an application’s memory reference behavior and thus significantly reduce the design space. While epoch profiles help to provide insight into the behavior of a single application, developing an understanding of a number of applications in the presence of area and core count constraints presents additional challenges. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Epoch-based microarchitectural analysis</i> is presented as a better way to understand the trade-offs for memory-bound applications in the presence of these physical constraints. Through epoch profiling and optimization, one can significantly reduce the multidimensional design space for hardware/software optimization through the use of high-level model-driven techniques.

Parallelization of Molecular-Dynamics Simulations Using Tasks

ABSTRACTThis article discusses novel algorithms for molecular-dynamics (MD) simulations with short-ranged forces on modern multi- and many-core processors like the Intel Xeon Phi. A task-based approach to the parallelization of MD on shared-memory computers and a tiling scheme to facilitate the SIMD vectorization of the force calculations is described. The algorithms have been tested with three different potentials and the resulting speed-ups on Intel Xeon Phi coprocessors are shown.

An Efficient Gauss--Newton Algorithm for Symmetric Low-Rank Product Matrix Approximations

We derive and study a Gauss--Newton method for computing a symmetric low-rank product $XX^{{T}}$, where $X \in{\mathbb{R}}^{n\times k}$ for $k<n$, that is the closest to a given symmetric matrix $A \in{\mathbb{R}}^{n\times n}$ in Frobenius norm. When $A=B^{{T}} B$ (or $BB^{{T}} $), this problem essentially reduces to finding a truncated singular value decomposition of $B$. Our Gauss--Newton method, which has a particularly simple form, shares the same order of iteration-complexity as a gradient method when $k \ll n$, but can be significantly faster on a wide range of problems. In this paper, we prove global convergence and a $Q$-linear convergence rate for this algorithm and perform numerical experiments on various test problems, including those from recently active areas of matrix completion and robust principal component analysis. Numerical results show that the proposed algorithm is capable of providing considerable speed advantages over Krylov subspace methods on suitable application problems where high-accuracy solutions are not required. Moreover, the algorithm possesses a higher degree of concurrency than Krylov subspace methods, thus offering better scalability on modern multi-/many-core computers.