Model For MOS Devices Research Articles

A low-power low-noise amplifier with high CMRR for wearable healthcare applications

Low-noise and low-power operation are important parameters of amplifier intended for wearable healthcare applications. However, along with these parameters the amplifier must be able to deliver high Common Mode Rejection Ratio (CMRR) for mitigating the effect of 50/60 Hz interference. This paper reports capacitively coupled-capacitive feedback amplifier based on Self Cascode Current Mirror-II (SCCM-II) Operational Transconductance Amplifier (OTA). The obtained results for proposed SCCM-II OTA based amplifier shows gain of 39.79 dB, input referred noise of 2.64 μVrms, bandwidth of 0.794-343.4 Hz, area consumption of 0.154 μm2, power consumption of 2.54 μW with ±0.9 V supply. The noise efficiency factor and CMRR values for proposed amplifier are 3.87 and 122.1 dB, respectively. In-depth theoretical interpretations and mathematical modeling of amplifier are validated in 0.18μm standard CMOS process using BSIM3V3 MOS device models. The Gaussian distribution plots of proposed amplifier for 200 Monte-Carlo iterations infer mean values for gain and CMRR are 39.79 dB and 112.96 dB which are very close to their nominal values. The proposed amplifier has been compared with conventional approach as well as with literature and improvement in results is observed in terms of input referred noise, power and CMMR. These advantages of the proposed amplifier make it suitable for non-invasive wearable healthcare applications.

Advances in Inversion Channel Mobility Model for 4H-SiC MOS Devices

Advances in Inversion Channel Mobility Model for 4H-SiC MOS Devices

An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

Design and simulation of pseudo-resistor with extremely high linearity for an improved neural signal recording.

Design of a pseudo-resistor (PR) structure based on a bulk driven quasi floating technique is presented, which not only provides a high value of resistance (≈1 TΩ) over a wider voltage swing of -1 V to 1 V, but also displays extremely high linearity. The same is useful for accurate amplification and recording of neural signals for better diagnosis of many chronic diseases. PR design reported in this paper has been simulated in 0.18 µm technology with BSIM3V3 MOS device models in the 6M1P standard process. The proposed PR has been simulated for its accuracy through its use in the design of the neural amplifier with a display of better performance than earlier reported work.

A New Approach for VDMOSFETs’ Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress

In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model.

Analytical Modelling and Design of CMOS Low-Noise Amplifier (LNA) with Electro-static Discharge Protection

ABSTRACTElectrostatic discharge (ESD) protection devices can have an adverse effect on the performance of RF circuits. This paper presents an analytical method to assess the performance changes of a CMOS low-noise amplifier (LNA) which incorporates ESD protection, when gate and source inductors and are optimally designed. Using a single capacitor model for diode ESD and an accurate MOS device model, a detailed analysis of the LNA design is presented. It has been confirmed analytically that the major changes in the characteristics of an LNA when connected with ESD protection is in input impedance and forward gain. Using a 0.25 µm UMC process parameter, ESD diode capacitance was calculated. By knowing the diode capacitance, a simple analytical procedure is given to determine series inductances and , which will provide optimal 50 Ω input impedance at the operating frequency of 2.4 GHz. Using these values of , , and , a common source CMOS LNA has been designed and fabricated in the 0.25 µm CMOS process. An optimum device size is used to minimize noise figure. Excellent agreement between simulation and measurement for all four -parameters of the LNA from 2.3 to 2.5 GHz has been achieved with a 2.1 dB minimum noise figure, for power consumption of 13.25 mW.

A low power cryogenic 512 × 512-pixel infrared readout integrated circuit with modified MOS device model

A low power cryogenic readout integrated circuit (ROIC) for 512×512-pixel infrared focal plane array (IRFPA) image system, is presented. In order to improve the precision of the circuit simulation at cryogenic temperatures, a modified MOS device model is proposed. The model is based on BSIM3 model, and uses correction parameters to describe carrier freeze-out effect at low temperatures to improve the fitting accuracy for low temperature MOS device simulation. A capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CDS) configuration is employed to realize a high performance readout interfacing circuit in a pixel area of 30×30μm2. Optimized column readout timing and structure are applied to reduce the power consumption. The experimental chip fabricated by a standard 0.35μm 2P4M CMOS process shows more than 10MHz readout rate with less than 70mW power consumption under 3.3V supply voltage at 77–150K operated temperatures. And it occupies an area of 18×17mm2.

A simplified post-soft-breakdown current model for MOS devices

Based on the tunneling current model, a simplified current model is developed for MOS devices after soft breakdown (SBD). The post-soft-breakdown current consists of modified direct tunneling current and Fowler Nordheim (FN) tunneling current. Considering the change of gate oxide after soft breakdown, impacts of soft breakdown on the dielectric constant, and effective electron mass of the gate oxide are discussed, and their values are obtained by fitting simulation results to experimental data. It is found that the effective electron mass is decreased after soft breakdown due to damaged oxide, while the dielectric constant is increased after soft breakdown due to interface distortion. In this way, the leakage current after soft breakdown can be accurately calculated. The validity of the proposed model is confirmed by experimental results.

Self-consistent 2D compact modeling of nanoscale bulk MOSFETs

In this paper, a closed-form analytical model for bulk MOS devices is presented, which calculates the device current from a 2D analytical solution of Poisson’s equation with self-consistently taking into account the inversion charge in the channel. The followed analytical technique for calculating the potential barrier height is highly structure oriented and valid from below to above threshold device operation. A charge-controlled current equation including hydrodynamic effects is derived which results in a model with excellent scalability. It is very close to device physics without the need to introduce numerical fitting parameters.

A New and Improved Physics-Based Model for MOS Transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.

Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.

An approach for quantum mechanical modeling and simulation for MOS devices, covering the whole operation region

A quantum mechanical (QM) approach for modeling and simulation of MOS devices, covering the whole operation region, was proposed. This formulation is applicable continuously from the subthreshold to the saturation regions, since it exactly treats the QM effects on the in-depth distribution of the gate induced carriers in the channel by solving one dimensional Poisson equation and Schrödinger equation self-consistently and it treats the lateral drift–diffusion transport using quasi-Fermi potential. A QM simulator was implemented using this QM approach. This QM simulator was verified by classical three-dimensional device simulator, CADDETH, in the whole range of operation of bulk MOSFET with low dopant density where QM effect is negligible. The QM simulation elucidated that the threshold voltage shift in thin SOI MOSFETs in saturation region as well as in linear region results from energy shift of the lowest conduction electron level and effective increase of gate oxide thickness.

An analytical subthreshold current model for pocket-implanted NMOSFETs

An analytical subthreshold current model for metal oxide semiconductor field effect transistors (MOSFETs) with pocket implantation is presented. The model is developed based on considering an averaged localized pileup of channel dopants near the source and drain ends of channel to account for the pocket implantation effect and to derive the channel potential using a pseudo-two-dimensional (2-D) method. This, together with the conventional drift-diffusion theory, leads to the development of a subthreshold current model for pocket-implanted MOS devices. Model verification is carried out using data measured from a set of pocket-implanted NMOSFETs fabricated from a 0.17-/spl mu/m, DRAM process. Very good agreement is obtained between the model calculations and measurement results.

A capacitance–voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge

We present a model for simulating the capacitance–voltage ( C– V) characteristics of polysilicon-gated MOS devices with thin oxides. The model includes substrate quantization effects through a modification of the total semiconductor charge. Therefore, solutions for C– V can be quickly obtained without the computational burden of solving over a physical grid. The model includes polysilicon depletion by self-consistently solving the charge balance equation. We conclude with comparisons of the C– V characteristics obtained with this model and those obtained by self-consistent solutions to the Schrödinger and Poisson equations. Good agreement was observed over a wide range of oxide thickness (2.0–15.0 nm) and substrate doping (10 15–10 18 cm −3).

Direct tunneling current model for MOS devices with ultra-thin gate oxide including quantization effect and polysilicon depletion effect

An efficient direct tunneling current model is presented for the ultra thin gate dielectric MOS structure. The tunneling current is modeled by including the inversion layer quantization effect with a finite potential barrier height as the boundary condition and the modified WKB method for calculating the transmission probability. The model is in good agreement with the full quantum calculation and the experiments. The results indicate that the finite boundary condition has to be considered for the ultra thin gate dielectric and the gate dielectric materials with lower barrier height. This model is accuracy and computational efficient and suitable to be used in characterized the sub-100 nm MOSFET with gate oxide below 2.0 nm.

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.

Modelling technique for uni-directional HV MOSdevices based on BSIM3v3

A SPICE model for bi-directional HV MOS devices based on BSIM3v3 is extended by adopting a new parameter extraction method for modelling uni-directional HV MOS devices.

A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling

A new definition of MOSFET threshold voltage is proposed, namely, the "critical-current at linear-threshold" method, which has a unique solution and is very simple to measure. This definition gives consistent values of threshold voltage for different regions of operation at long channel, and contains the information on short-channel effects at short channel, which is very useful for deep-submicron MOS device characterization and modeling. The proposed method effectively removes ambiguity of de facto industry standard of the constant-current method for MOS threshold voltage.

Analytical capacitance model for submicron accumulation-mode SOI MOS devices

This paper presents an analytical capacitance model for submicron accumulation-mode SOI MOS devices. Based on the study, compared to the inversion-mode device, the accumulation-mode SOI MOS device has a gradual transition in C GS from subthreshold to accumulation due to the effect of the buried channel above the buried oxide.