High-k dielectric insulators are required to reduce leakage and increase transistor performance. They are able to impact the mobility of carriers in transistors positively, leading to better device performance in advanced transistor architecture. Nevertheless, an in-depth analysis of how high-k dielectric insulators influence transistor characteristics must be carried out to determine their suitability. The objective of this study is to investigate the impact of high-k insulators towards electrical properties of junctionless double gate strained transistor. The simulation works is done using process/device simulator Silvaco Athena/Atlas. Based on the retrieved results, the magnitude of I<sub>ON</sub>, on-off ratio, g<sub>m</sub>, and C<sub>int</sub> for TiO<sub>2</sub>-based device are approximately 63%, 99%, 62%, and 89% respectively higher than the lowest permittivity material-based device. The TiO<sub>2</sub>-based device also exhibits the lowest magnitude in I<sub>OFF</sub> and SS compared to others. However, a significant degradation in f<sub>T</sub> magnitude have been observed for TiO<sub>2</sub>-based device significantly due to its large capacitances
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