MNOS Memory Transistors Research Articles

MNOS Retention-Endurance Characteristics Enhancement Using Graded Nitride Dielectric

Supported by a microscopic model, a graded nitride dielectric MNOS memory transistor has been developed. In this paper, improvements of MNOS endurance-retention characteristics of the graded nitride MNOS memory transistor are discussed in view of the device model. Nitride dielectrics fabricated with APCVD and LPCVD processes are studied.

N-Channel Si-gate process for MNOS EEPROM transistors

An n-channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900° C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t w = 10 ms and an erase time of t e = 100 ms. The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10 7 pulses of ±25 V, 100 μs corresponding to approx. 10 4 write/erase cycles showed no time dependence for the decay rate over the time of 10 5 min in which retention measurements were made.

The gated-access MNOS memory transistor

A new modification of the MNOS transistor results in significant advantages. It combines a depletion-mode channel with electrically separate electrodes over the memory portion and the fixed threshold portion of a step-gate device. This elimnates read disturb during interrogation; therefore, much longer retention is now possible. It also decreases access time within an LSI array. For block-written EAROM's, a new form of dynamic inhibit makes memory array isolation unnecessary. These and other improvements obtained with this structure do not require new processes or a significant increase in size.

MNOS Traps and Tailored Trap Distribution Gate Dielectric MNOS

A microscopic model of the memory traps has been developed that is consistent with the known properties of the MNOS devices. In this model, the memory traps are attributed to the silicon dangling bonds in the silicon nitride. The resultant trap center is amphoteric in nature, possessing either a positively or a negatively charged state. The dangling bond model is applied towards the interpretation of MNOS properties, including retention and endurance. In addition, the model was used to explain and further develop the tailored-trap-distribution gate-dielectric MNOS memory transistor.

Charge-Coupled Device (CCD) Adaptive Discrete Analog Signal Processing

A CCD adaptive signal processor is described which uses a so-called "clipped-data" least mean square (LMS) error algorithm to optimize the selection of tap weights in a CCD filter. A detailed description of a 16-tap monolithic silicon CCD analog adaptive filter is also presented. The filter is comprised of a basic linear combiner formed with a nondestructively tapped CCD analog delay line and electrically reprogrammable MOS analog conductances as the tap weights. Two methods of varying the analog conductance are discussed: 1) variable V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> with fixed threshold voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and 2) variable V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> with fixed V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> . The former is performed with a CCD bidirectional charge control weight adjustment, whereas the latter is accomplished with MNOS memory transistors. To demonstrate the feasibility of adaptive analog signal processing, a 2-tap weight CCD adaptive filter is described and experimental results presented. Applications include optimum filtering, prediction, noise cancellation, and system modeling.

The influence of nitride thickness variations on the switching speed of MNOS memory transistors

The influence of nitride thickness variations on the switching speed of MNOS memory transistors is examined. The switching time constant is calculated as a function of the nitride thickness using a model of modified Fowler-Nordheim injection. The calculated characteristics compare well with measured characteristics and show a strong dependence on the nitride thickness.

ChemInform Abstract: THE EFFECTS OF HYDROGEN CHLORIDE RESIDUAL TREATMENT ON MNOS MEMORY TRANSISTORS

Chemischer InformationsdienstVolume 9, Issue 38 Physical Inorganic Chemistry ChemInform Abstract: THE EFFECTS OF HYDROGEN CHLORIDE RESIDUAL TREATMENT ON MNOS MEMORY TRANSISTORS R. M. MCLOUSKI, R. M. MCLOUSKISearch for more papers by this authorM. C. PECKERAR, M. C. PECKERARSearch for more papers by this authorJ. J. SCHREURS, J. J. SCHREURSSearch for more papers by this author R. M. MCLOUSKI, R. M. MCLOUSKISearch for more papers by this authorM. C. PECKERAR, M. C. PECKERARSearch for more papers by this authorJ. J. SCHREURS, J. J. SCHREURSSearch for more papers by this author First published: September 19, 1978 https://doi.org/10.1002/chin.197838015Read the full textAboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat No abstract is available for this article. Volume9, Issue38September 19, 1978 RelatedInformation

Measurement of the effect of write-erase cycling on noise in MNOS memory transistors

p-channel MNOS memory transistors with 25-Å oxide, 550-Å nitride are investigated. Changes in memory characteristics such as high-conductivity and low-conductivity threshold voltages are examined as a function of the number of write-erase cycles taking the amplitude and the duration of the pulses as parameters. Simultaneous measurements of the channel carrier mobility and low-frequency noise spectrum give new information. Changes in noise properties after cycling depend on the amplitude and duration of the write-erase pulses. Beyond about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> write-erase cycles the memory window decays, the channel carrier mobility drops, while the noise exhibits a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/f^{2}</tex> spectrum in the lowest frequency region. Experimental results are interpreted by the formation, during cycling, of a high density of hole traps distributed in energy and located inside the insulators near the oxide-nitride interface.

1 K-bit nonvolatile semiconductor read/write RAM

A 1024-bit nonvolatile semiconductor read/write random access memory (RAM) is described which is operated as a static RAM under a stable power supply, and the stored information can be transferred into MNOS memory transistors for nonvolatile storage when the power supply is turned off. A nonvolatile flip-flop cell consisting of 8 MOS transistors and 2 MNOS transistors is used on the basis of p-channel silicon gate technology. The chip size is 4.36 × 5.50 mm2. Typical read access time is 900 ns, and the stored data can last for more than one year. Endurable power on and off cycles are 105cycles.

Radiation-hardened MNOS RAM technology

Development of a fast writing MNOS memory transistor along with a compatible hardened oxide peripheral transistor has led to successful fabrication of radiation-hardened MNOS RAM circuits. Using a 2.8-µs write cycle and 1.0-µs access time, 24-h retention and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> write cycle endurance have been demonstrated on a 256-bit MNOS RAM.

The Effects of HCl Residual Treatment on MNOS Memory Transistors

not Available.

Avalanche-tunnel injection in MNOS transistor

Features and mechanism of the combination of hot electron injection and direct tunneling injection in p-channel MNOS memory transistors have been studied. It is made clear that injection near reversely biased source and drain junctions is hot electron injection, whereas injection in the middle of the channel region is mostly by direct tunneling, because the potential at the surface approaches that of source and drain due to the current flow distribution during avalanching. A two-dimensional Poisson's equation has been solved to quantitatively describe the avalanche-tunneling and compared with experimental results. The features of the avalanche-tunneling are in the single polarity writing for both "1" and "0" logic levels, which make it possible to implement EAROM and nonvolatile RAM without substrate isolation between the cell and the periphery.

Endurance of thin-oxide nonvolatile MNOS memory transistors

A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

One of the most important degradation effects observed in MNOS memory transistors is a negative shift of the threshold window. This negative shift is caused by a strong increase of the density of Si-SiO2 surface traps. This effect has been proposed to be caused by the same effect that is observed in MOS devices subjected to negative-bias stress (NBS). In this paper, a detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25–125 °C) and fields (400–700 MV/m) comparable to those used in MNOS devices is presented. Two different behaviors are observed. At low fields the surface-trap density increases as t1/4 and at high fields it increases linearly with the stress time t. The low-field behavior is temperature and field dependent and the zero-field activation energy is determined to be 0.3 eV. The high-field behavior is strongly field dependent but independent of temperature. A physical model is proposed to explain the surface-trap growth as being diffusion controlled at low fields and tunneling limited at high fields. A comparison with MNOS degradation is made and it was found to be related to the t1/4 behavior mentioned above.

Charge transfer by direct tunneling in thin-oxide memory transistors

Charge transfer by direct tunneling in thin-oxide MNOS memory transistors is carefully examined and the similarities and dissimilarities between different models is shown. The consequences of different assumptions concerning the tunneling probability, surface states, and trap distributions are investigated, and directions for future work are discussed.

Fully decoded MNOS storage arrays in ESFI MOS technology

The operation of MNOS memory transistors realized in thin epitaxial silicon films on insulators (ESFI) is described for writing, erasing, and reading, and their behavior is explained by means of the so-called storage characteristics. From exploratory matrices with 2/spl times/2 elements the expected data of a 4-kbit chip are estimated.

Degradation of MNOS memory transistor characteristics and failure mechanism model : M. H. Woods and J. W. Tuska. 10 th IEEE Annual Proceedings, Reliability Physics (1972), p. 120

Degradation of MNOS memory transistor characteristics and failure mechanism model : M. H. Woods and J. W. Tuska. 10 th IEEE Annual Proceedings, Reliability Physics (1972), p. 120

MNOS memory transistors in simple memory arrays

The basic properties of MNOS memory transistors as digital memory elements are reviewed. Optimization procedures for obtaining maximum memory retention are presented and possible arrangements of memory transistors in simple arrays and writing and reading procedures for such arrays are discussed.

Properties of MNOS structures

The properties of thin oxide MNOS structures are studied. An analytical theory for the switching time constant is derived and curves of the switching time constant versus the nitride field are computed. These curves are useful in the design of MNOS-memory transistors. The theory is compared with experiments. The normal current in the thin oxide MNOS structures is assumed to be a modified Fowler-Nordheim current. At small oxide thicknesses and low nitride field, an additional current is shown to exist that is attributed to direct tunneling into traps in the nitride. The discharge of MNOS structures is briefly discussed and is shown to be due to a direct tunneling of charge carriers from traps in the nitride into the semiconductor.