Μm Bipolar-CMOS-DMOS Process Research Articles

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

The integrated fast short-circuit protection technique with soft turn-off for SiC MOSFET

In this paper, the integrated fast short-circuit protection technique with soft turn-off is proposed for SiC (silicon carbide) MOSFET. Two short-circuit faults, HSF (hard switching fault) and FOF (flashover fault), can be judged by detecting EMI (electromagnetic interference) noises of SiC MOSFET. When there are short-circuit faults for SiC MOSFET, the soft turn-off is initiated to reduce EMI noises and protect SiC MOSFET. The proposed fast short-circuit protection technique is realized on the chip and is verified in a 0.18 μm BCD (Bipolar-CMOS-DMOS) process. Simulation results show that the proposed short-circuit protection has a fast response speed and then SiC MOSFET is turned off slowly when there are HSF and FOF. Therefore, the proposed fast short-circuit protection technique can be well applied for SiC MOSFETs, making SiC MOSFETs safely used in HV (high-voltage) and high current applications.

Design Techniques of Sub-ns Level Shifters With Ultrahigh dV/dt Immunity for Various Wide-Bandgap Applications

In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μm bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/(μm × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μm BCD process, and the propagation delay can be decreased by more than 60%.

3–12-V Wide Input Range Adaptive Delay Compensated Active Rectifier for 6.78-MHz Loosely Coupled Wireless Power Transfer System

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3-12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved.

A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control

Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 μm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A.

Optimization of lateral double-diffused MOS transistors in 0.18 µm bipolar-CMOS-DMOS technology for wide-voltage applications

The reduced-surface-field-type lateral double-diffused MOS (LDMOS) structure, which is the key element used in the power device of the bipolar-CMOS-DMOS (BCD) process, was optimized for a wide voltage range of 20–60 V class in the 0.18 µm BCD process. The on-state resistance (Ron) characteristics to the drain-to-source breakdown voltage (BVdss) have been improved by optimizing the n-drift conditions and related design rules and the reliable safe operating area (SOA) of the device has also been secured for the 20–30 V class LDMOS device. In order to optimize the 40–60 V class LDMOS device, the n-drift drain buffer and low voltage-threshold voltage for the p-channel device implant were introduced and the reliable SOA was obtained while the excellent Ron characteristics showed up to the 60 V class. The final trade-off (Ron versus BVdss) characteristics of the LDMOS fabricated under the newly proposed 0.18 µm BCD process have shown competitive characteristics in the wide voltage range for the various applications.

Design and Measurement of a 1-kBit eFuse One-Time Programmable Memory IP Based on a BCD Process

We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18µm BCD process is 283.565 × 524.180µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1V less than that of the p+ gate poly-silicon.

A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.