Mixed-level Approach Research Articles

Advancing Interdisciplinary Teamwork: Processes Supporting High-Quality and Innovative Performance

To advance our understanding of interdisciplinary teamwork in complex organizations, we present four papers that leverage diverse methods to identify processes that bridge the gaps across disciplines and support quality and innovation. The papers include a broad range of specific healthcare settings, countries (e.g., United States, Israel), and using different research methodologies and analyses (e.g., systematic literature review, qualitative, quantitative, multi-sourced surveys, multilevel models). We identify multiple teamwork processes (e.g. problem solving, mechanized patient follow-up, professional cooperation, and cooperation with patients) that are common across interventions and settings. Specifically, we begin with the current state of empirical evidence by presenting a systematic review that identifies roles and teamwork processes that improve quality outcomes in the peri-operative period. We follow with a paper exploring the paradox of lean management and innovation and if hospitals differ from R&D in their association with quality and innovation. We continue with a paper covering the different impacts of social compared to functional team processes to improve quality of care. We end with a qualitative investigation of individual compared to collective improvisation. Together these studies help advance the science of interdisciplinary teamwork towards supporting high-quality care and innovative performance. Team Processes to Improve Quality in Perioperative Cancer Care: A Systematic Review Presenter: Karleen F. Giannitrapani; Stanford U. / VA Palo Alto The Paradox of Lean Management and Innovation: Are Hospitals Different than R&D? Presenter: Tal Katz-Navon; Arison School of Business, Reichman U. (IDC), Israel The association between social and functional integration and care quality Presenter: Micah Aaron; Harvard Medical School Improvisation as Defense Under Crisis: Applying A Mixed-Level Approach in Response to Covid-19 Presenter: Zhanna Novikov; Stanford U.

Accounting for coherent effects in the ray-tracing of light-emitting diodes with interface gratings via mixed-level simulation

Ray-tracing (RT) has long been the workhorse technique for analyzing light-emitting diode (LED) dies and packages and has led to significant improvements in extraction efficiency and beam shaping. However, to achieve further enhancements, nano-/microscale features such as patterned substrates and surface textures have been explored. The coherent effects arising from these near/subwavelength features are difficult to include in the RT of the packaged device. We show that under certain conditions these effects can have a significant impact on LED performance, especially if back-reflectors are present. Furthermore, we demonstrate that coherence must be accounted for even in structures that would otherwise be considered as having relatively large feature sizes, such as gratings with periods many times the wavelength. We present comparisons between the optical responses of prototypical periodically patterned substrates modeled with RT alone and with a mixed-level approach that combines RT and rigorous electromagnetic simulation, such as rigorous coupled wave analysis and finite-difference time-domain. Several examples with varying lateral periods are computed with both methods. It is shown that these results may differ, and that these differences can be significant if back reflection is present. We conclude that a mixed-level approach is an efficient and accurate method to model light extraction in modern LEDs.

Mixed-level optical simulations of light-emitting diodes based on a combination of rigorous electromagnetic solvers and Monte Carlo ray-tracing methods

Over the last two decades, extensive research has been done to improve light-emitting diodes (LEDs) designs. Increasingly complex designs have necessitated the use of computational simulations which have provided numerous insights for improving LED performance. Depending upon the focus of the design and the scale of the problem, simulations are carried out using rigorous electromagnetic (EM) wave optics-based techniques, such as finite-difference time-domain and rigorous coupled wave analysis, or through ray optics-based techniques such as Monte Carlo ray-tracing (RT). The former are typically used for modeling nanostructures on the LED die, and the latter for modeling encapsulating structures, die placement, back-reflection, and phosphor downconversion. This paper presents the use of a mixed-level simulation approach that unifies the use of EM wave-level and ray-level tools. This approach uses rigorous EM wave-based tools to characterize the nanostructured die and generates both a bidirectional scattering distribution function and a far-field angular intensity distribution. These characteristics are then incorporated into the RT simulator to obtain the overall performance. Such a mixed-level approach allows for comprehensive modeling of the optical characteristic of LEDs, including polarization effects, and can potentially lead to a more accurate performance than that from individual modeling tools alone.

System-level Modeling of Silicon Microphones Including Distributed Effects

We present a hierarchical modeling methodology, which combines short simulation times with the attention to detail as provided by finite element-based techniques. It enables predictive simulation of micro-devices even if exhibiting complex geometries like the MEMS microphone considered in this work. The challenge to properly account for mechanical, electrical and fluidic effects including their respective couplings has been solved by applying a mixed-level approach realized in a commercial system-level simulation environment. This enables to systematically include not only lumped but also distributed effects, like viscous damping and inhomogeneously distributed electrostatic forces. Applying the calibrated and validated model we obtain important microphone characteristics and, moreover, insights into distributed phenomena affecting the device operation. Hence, this constitutes a powerful tool for re-design and optimization as well as for the development of new prototypes.

Efficient multi-level fault simulation of HW/SW systems for structural faults

In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate- and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.

Automated extraction of multi-energy domain reduced-order models demonstrated on capacitive MEMS microphones

We present a methodology to systematically extract efficient and physically-based reduced-order models based on a mixed-level simulation approach and demonstrate its practicality for the design of a capacitive MEMS microphone. The method has been implemented in a MATLAB toolbox. Starting from a FEM discretization, it enables the automated generation of mixed-level VHDL-AMS based macromodels, which can be straightforwardly fed into a standard circuit simulator. The whole model generation process is described in all details. The resulting macromodels are highly efficient and moreover, in contrast to other equivalent network approaches, physically-based. Therefore they allow for the predictive simulation of microstructures with complex geometry, as it is demonstrated by the numerical analysis of a capacitive microphone.

Accurate system-level damping model for highly perforated micromechanical devices

Abstract We present an efficient methodology to set up reduced order models for damping effects in large-scale, highly perforated microdevices. We start from the mixed-level approach to the modeling of viscous damping in microdevices as reported in recently published work [Sens. Actuators A 97–98 (2002) 193], extend it to torsionally moving devices and derive a methodology that reduces the degrees of order for highly perforated microdevices considerably without losing accuracy. The resulting damping model can be easily incorporated into system-level models of entire microsystems and therefore is well-suited for fast and efficient design studies of complex microsystems. The method has been successfully applied to a highly perforated torsional switch which was fabricated using industrial CMOS technology. The resulting model is very efficient and the excellent agreement with experimental data shows the high accuracy of the method, which is necessary for predictive simulation.

Partitioning and analysis of static digital CMOS circuits

Performance optimization of automatic test pattern generation (ATPG) algorithms has received considerable attention. While the application of high-performance algorithms is often limited to simple gates such as AND's, OR's, and XOR, the cell libraries of silicon vendors usually contain more sophisticated structures. To deal with this problem, we present a library independent algorithm for the partitioning and analysis of static digital CMOS circuits described at the switch level. The algorithm recognizes inverters, NANDs, and NORs. It also checks whether a partition can set its output to a high impedance state, thus being capable of partitioning large bus structures with tristate gates. Our approach supports existing ATPG algorithms at the gate level. Moreover, it allows a mixed-level approach for ATPG using detailed fault models at the switch level for whatever partitions it is necessary. Our implementation processes in the order of 2000 transistors per second. This is for circuits containing combinational and sequential logic on a state-of-the-art workstation. We processed complete chips with up to 72000 transistors, which is clearly adequate for practical purposes.

Computer-aided design and scaling of deep submicron CMOS

A simulation tool-box and its applications to computer-aided design and scaling of deep-submicron CMOS are presented. The simulation tools are grouped around a mixed level approach and cover a wide range of applications. Due to the mixed-level approach, fast table models and accurate numerical models can be combined simultaneously in a single circuit simulation. Device and circuit characteristics can be accurately represented as functions of technical parameters, even in the deep-submicron region. The application of the toolbox is demonstrated for some examples from the fields of device design and SRAM scaling. The gate-drain overlap and junction depth of 0.4- mu m devices are optimized with respect to circuit performance and device degradation. Different drain structures and supply voltages for 0.25- mu m devices are compared. Scaling of CMOS SRAM's from 0.7 to 0.4 mu m and finally to 0.25- mu m gate length is simulated. The relevance of device structure, design rules, and supply voltage for speed, power dissipation, and chip area are pointed out and their influence on circuit performance predicted.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A tool for hierarchical test generation

An extended system MSST (MIMOLA software system test generator), and its algorithms for automatic test generation are presented. In a hierarchical, mixed-level approach (from gate to system level) test patterns for sequential circuits and test programs for external testing or self-testing (diagnostics) of microprocessor boards or processor systems can be generated automatically. In a complete hierarchy lower bounds for test coverage are easily computable. The MIMOLA design system (including MSST) has been installed on VAX, APOLLO, SUN, and several other host machines. Several production line test applications show good results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Binary Decision Diagrams (BDDs) For TheTest Pattern Generation

Since fault-free CMOS digital integrated circuits are characterized by very low values of quiescent power-supply current (IDDQ), and the most part of their faults provoke abnormally high values of such current, IDDQ testing is one of the most effective way of testing them. The classical test pattern generation at the logic level is not accurate enough for IDDQ testing, because the values of actual faulty current must be estimated and compared with the accuracy of the current monitor to decide on the fault detection; on the other side, electrical-level approaches are not feasible for VLSI ICs. The test pattern generation for IDDQ testing can be effectively performed with a mixed-level approach, featuring boolean manipulation by means of BDDs at the logic level, and using look-up tables for electrical-level data obtained by preliminary SPICE simulations on library cells.