MIT Lincoln Lab Research Articles

Low-Temperature Superconductor rf-SQUIDs-Based Fully Integrated Reflective-Type Analog Phase Shifter for Quantum Applications

This article presents a low-temperature superconductor (LTS)-based microwave phase shifter. The device utilizes a superconducting hybrid coupler monolithically integrated with two tunable reflective loads. An array of radio frequency superconducting quantum interference devices (rf-SQUIDs) is used to achieve inductive tuning in reflective loads, resulting in a broadband true time delay phase shift. The rf-SQUIDs are current controlled using an on-chip dc bias circuitry. The proof-of-concept fabricated device provides excellent RF performance in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${X}$ </tex-math></inline-formula> - and Ku -band with a phase shift of 49° at 10 GHz and 67° at 15 GHz. The insertion loss is < 1.5 dB for the entire range from 8 to 18 GHz. The methods to further improve the obtained phase shift are discussed. The overall device has a chip footprint of 0.6 mm2 and is fabricated using MIT-Lincoln Lab (MIT-LL) SFQ5ee eight-layer Niobium (Nb)-based superconducting fabrication process.

Focusing on motion and averaging the diagonal: Lisa Zurk’s many contributions to passive sonar array processing

Lisa Zurk’s numerous contributions to passive sonar signal processing include motion compensation and regularizing sample covariance matrices (SCM) in snapshot deficient environments. While working at MIT Lincoln Labs, Lisa and colleagues compared the performance of several motion compensation methods including mode-based rank reduction and target motion compensation, or focusing, on the Santa Barbara Channel Experiment dataset [Zurk, Lee &amp; Ward, JASA, 2003]. Later at Portland State, Jorge Quijano and Lisa developed methods for regularizing the SCM through Toeplitz averaging, followed by maximum entropy extrapolation of the SCM to additional lags, [Quijano &amp; Zurk, JASA, 2017]. Toeplitz regularization found significant application in developing “augmented covariance matrices” for DOA estimators on sparse arrays. This talk reviews some of Lisa’s contributions to adaptive beamforming and highlights how some of her contributions inspired research in the UMass Dartmouth Signal Processing Group. [Work supported by ONR Code 321US.]

Accurate Small Signal Simulation of Superconductor Interconnects in SPICE

Superconductor electronics is gaining traction as the increasing density of integration of recent and future digital circuits pushes the limits of available simulation models. Designers often make assumptions in the behavioral models of circuit elements when simulating circuits. For instance high-frequency effects have been neglected so far in the design of superconductor digital circuits, while much has been done in the past to model them. Indeed these effects had little influence on the accuracy of digital circuits simulations until recently. The increase in clock frequency, combined with longer paths between cells and higher yield requirements for large scale circuits fabrication, has led to the need of more accurate models, including in particular high frequency effects such as quasi-particle losses. To do so, this work uses a state-space model that describes the circuit under study with internal state variables and a set of first-order differential equations. We extract the state-space model while analytically enforcing the DC requirements of superconductors that are required to account for flux-trapping. The model accurately traps flux at DC, and given the model is fitted with enough poles, the high-frequency effects are also accurate relative to the reference model. The high-frequency effects have been investigated on a practical circuit: a long-distance Passive Transmission Line (PTL) designed for the high-density MIT Lincoln Labs SFQ5ee process. Results obtained in the time domain allow to observe the effects of dispersion of pulses traveling on long paths of PTLs. Indeed the energy of voltage pulses is sufficient to break Cooper pairs for the highest clock frequencies.

A Framework for Enhancing Deep Neural Networks Against Adversarial Malware

Machine learning-based malware detection is known to be vulnerable to adversarial evasion attacks. The state-of-the-art is that there are no effective defenses against these attacks. As a response to the adversarial malware classification challenge organized by the MIT Lincoln Lab and associated with the AAAI-19 Workshop on Artificial Intelligence for Cyber Security (AICS'2019), we propose six guiding principles to enhance the robustness of deep neural networks. Some of these principles have been scattered in the literature, but the others are introduced in this paper for the first time. Under the guidance of these six principles, we propose a defense framework to enhance the robustness of deep neural networks against adversarial malware evasion attacks. By conducting experiments with the Drebin Android malware dataset, we show that the framework can achieve a 98.49\% accuracy (on average) against grey-box attacks, where the attacker knows some information about the defense and the defender knows some information about the attack, and an 89.14% accuracy (on average) against the more capable white-box attacks, where the attacker knows everything about the defense and the defender knows some information about the attack. The framework wins the AICS'2019 challenge by achieving a 76.02% accuracy, where neither the attacker (i.e., the challenge organizer) knows the framework or defense nor we (the defender) know the attacks. This gap highlights the importance of knowing about the attack.

ERSFQ Power Delivery: A Self-Consistent Model/Hardware Case Study

Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.

ERSFQ 8-Bit Parallel Arithmetic Logic Unit

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.

ERSFQ 8-bit Parallel Binary Shifter for Energy-Efficient Superconducting CPU

We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bi-directional SHIFT instruction of an 8-bit argument. It consists of a bi-direction triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ~ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of +/-16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within +/-10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter.

Development of an All-SFQ Superconducting Field-Programmable Gate Array

Recent advances in fabrication complexity and density-especially for the Institute of Advanced Industrial Science and Technology (AIST) advanced process 2 (ADP2) process and the MIT Lincoln Lab (MITLL) SFQ5ee process and beyond-allow the implementation of a superconducting field-programmable gate array (SFPGA) with sufficient complexity to host a number of different programmed functions. We discuss design choices for an all single flux quantum SFPGA targeting these modern processes, making heavy use of passive transmission line (PTL) layers they provide. Various configurations for lookup tables, basic logic elements and timing schemes are shown, and a viable switch block implementation is discussed. Academic FPGA electronic design automation (EDA) tools are repurposed for mapping Verilog hardware description language (HDL) functions to the chosen SFPGA design, whilst HDL and electrical simulations are used to show its correct operation. We show simulations for programming and the operation of an SFPGA, and discuss die size requirements for practical implementation.

Towards Intelligent Disaster Response Systems

Next Generation Incident Response System (NICS) is a platform developed by MIT Lincoln Lab that is currently being used in Macedonia by the Centre for Crisis Management (CCM). It allows coordination during natural disasters between first responders of various departments and allows them to use state of the art tools to communicate and share information. This research focuses on advancing the platform by introducing intelligent agents to the platform, based on machine learning techniques and natural language processing. Our goal is to leverage data generated in social media and feed NICS with automatically processed information from these media categorized in twelve different needs (categories). This paper presents the current state of our research, preliminary results and final goals.

High-Accuracy InductEx Calibration Sets for MIT-LL SFQ4ee and SFQ5ee Processes

The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.

A Hybrid Machine Learning Method for Intrusion Detection

Data security is an important area of concern for every computer system owner. An intrusion detection system is a device or software application that monitors a network or systems for malicious activity or policy violations. Already various techniques of artificial intelligence have been used for intrusion detection. The main challenge in this area is the running speed of the available implementations. In this research work, we present a hybrid approach which is based on the “linear discernment analysis” and the “extreme learning machine” to build a tool for intrusion detection. In the proposed method, the linear discernment analysis is used to reduce the dimensions of data and the extreme learning machine neural network is used for data classification. This idea allowed us to benefit from the advantages of both methods. We implemented the proposed method on a microcomputer with core i5 1.6 GHz processor by using machine learning toolbox. In order to evaluate the performance of the proposed method, we run it on a comprehensive data set concerning intrusion detection. The data set is called KDD, which is a version of the data set DARPA presented by MIT Lincoln Labs. The experimental results were organized in related tables and charts. Analysis of the results show meaningful improvements in intrusion detection. In general, compared to the existing methods, the proposed approach works faster with higher accuracy.

Performance Analysis of Intrusion Detection Systems Implemented using Hybrid Machine Learning Techniques

Intrusion Detection System (IDS) are said to be more effective when it has both high intrusion detection (true positive) rate and low false alarm (false positive). But current IDS when implemented using data mining approach like clustering, classification alone are unable to give 100 % detection rate hence lack effectiveness. In order to overcome these difficulties of the existing systems, many researchers implemented intrusion detection systems by integrating clustering and classification approach like k-means and Fuzzy logic, K-means and genetic algorithm, some of the researcher also tried use of Decision tree and Neural Network to detect unknown attacks. In this paper analysis of such Hybrid systems which are implemented by using the benchmark dataset compiled for the 1999 KDD intrusion detection contest, by MIT Lincoln Labs.

ERSFQ 8-Bit Parallel Adders as a Process Benchmark

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Analysis of Intelligent Classifiers and Enhancing the Detection Accuracy for Intrusion Detection System

In this paper we discuss and analyze some of the intelligent classifiers which allows for automatic detection and classification of networks attacks for any intrusion detection system. We will proceed initially with their analysis using the WEKA software to work with the classifiers on a well-known IDS (Intrusion Detection Systems) dataset like NSL-KDD dataset. The NSL-KDD dataset of network attacks was created in a military network by MIT Lincoln Labs. Then we will discuss and experiment some of the hybrid AI (Artificial Intelligence) classifiers that can be used for IDS, and finally we developed a Java software with three most efficient classifiers and compared it with other options. The outputs would show the detection accuracy and efficiency of the single and combined classifiers used.

An Overview of the Industry Initiatives Committee [Report of the Industry Initiatives Committee

The Industry Initiatives Committee (IIC) is a standing committee of the IEEE Antennas and Propagation Society. The Industry Initiatives Committee was formed in early 2010 as an ad hoc committee, with the vision and initiative of Prof. Robert Nevels, who was also the past President of the IEEE AP-S. During the early stages, Dr. Charles Rhodes provided the advice and support needed in the growth of the Industry Initiatives Committee. There were initially four members, and it has now 12 members from the international community of the Society. The Industry Initiatives Committee was approved as a standing committee of AP-S during the AdCom meeting in February 2012. The Industry Initiatives Committee is chaired by Dr. Sudhakar Rao, and has the fol lowing members: ? Sudhakar Rao, Northrop Grumman, USA (Chair) ? Isamu Chiba, MELCO, Japan ? Jay Guo, CSIRO, Australia ? Robert Hoferer, GD Satcom, USA ? Jay Kralovec, Harris, USA ? Nuria Llombart, Delft Technical University, The Netherlands ? Peter de Maagt, European Space Agency, The Netherlands ? Tom Milligan, Consultant, USA ? Aldo Petosa, Communications Research Corporation, Canada ? Charles Rhodes, Raytheon, USA ? Michael Shields, MIT Lincoln Labs, USA ? Hema Singh, National Aerospace Labs, India

High voltage GaN‐on‐silicon HEMT

AbstractM/A‐COM Technology Solutions has continued in the joint development efforts sponsored by the Department of Energy with MIT main campus and MIT Lincoln Labs to develop GaN on silicon three terminal high voltage/high current HEMT switching devices. The first year developmental goals were for a three terminal structure that has a reverse breakdown characteristic of &gt;1200 V and is capable of switching 10 amperes of current. An average three terminal breakdown of 1322 V was achieved on a single finger 250 µm GaN on silicon HEMT device utilizing a source connected field plate with a 4.5 µm drain region overlap. An individual device breakdown on a single finger 250 µm GaN on silicon HEMT device with a SCFP of &gt;1630 V was measured at a current of 250 µA (1mA/mm) – One of the highest yet reported for GaN on silicon in the industry. (© 2013 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%.

A Novel Approach to Detect Network Attacks Using G-HMM-Based Temporal Relations between Internet Protocol Packets

This paper introduces novel attack detection approaches on mobile and wireless device security and network which consider temporal relations between internet packets. In this paper we first present a field selection technique using a Genetic Algorithm and generate a Packet-based Mining Association Rule from an original Mining Association Rule for Support Vector Machine in mobile and wireless network environment. Through the preprocessing with PMAR, SVM inputs can account for time variation between packets in mobile and wireless network. Third, we present Gaussian observation Hidden Markov Model to exploit the hidden relationships between packets based on probabilistic estimation. In our G-HMM approach, we also apply G-HMM feature reduction for better initialization. We demonstrate the usefulness of our SVM and G-HMM approaches with GA on MIT Lincoln Lab datasets and a live dataset that we captured on a real mobile and wireless network. Moreover, experimental results are verified by -fold cross-validation test.

3D detector and electronics integration technologies: Applications to ILC, SLHC, and beyond

The application of vertically integrated (3D) electronics to particle physics has been explored by the our group for the past several years. We have successfully designed the first vertically integrated demonstrator chip for ILC vertex detection in the three-tier MIT-Lincoln Labs process. We have also studied sensor integration with electronics through oxide bonding and silicon-on-insulator technology. This paper will discuss the status of these studies and prospects for future work.