MIS Tunnel Diodes Research Articles

Analytical Modeling of the Temporal Response of the Transient Displacement Currents in MIS Tunnel Diodes Under Low-Voltage Operation

Analytical Modeling of the Temporal Response of the Transient Displacement Currents in MIS Tunnel Diodes Under Low-Voltage Operation

Enhanced coupling current in center MIS tunnel diode by effective control of the edge trapping in ring with Al2O3/SiO2 gate stack

Enhanced coupling current in center MIS tunnel diode by effective control of the edge trapping in ring with Al2O3/SiO2 gate stack

Study and Optimization of Two-State Transient Currents at Millisecond Time Scales in MIS Tunnel Diodes

Study and Optimization of Two-State Transient Currents at Millisecond Time Scales in MIS Tunnel Diodes

Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)

Metal-Insulator-Semiconductor tunnel diodes (MISTD) are widely used in modern integrated circuits, and have shown the potential in dynamic memory [1], [2]. To recognize the memory states more easily, efforts should be made to enhance the transient behavior. Recently, MISTD with ultra-thin metal surrounded gate (UTMSG) had been proposed in [3] and [4], presenting improved transient current and transient capacitance. In this work, we further modulated the proportion of surrounding gate, S, and found increased transient behavior for larger S.Fig. 1(a) and (b) illustrate the structure of UTMSG and planar MISTD, respectively. For UTMSG, the total gate is composed of a thick metal center gate and a resistive thin metal surrounding gate. Fig. 2 shows the process flow and the anodic oxidation system. For UTMSG, after defining the center gate by photolithography, dilute nitric acid was used to form a very thin aluminum oxide layer on the edge. 10 nm Al was then evaporated as the resistive surrounding gate. Table 1 lists the detailed parameters and the proportion of surrounding gate, S. Fig. 3(a) shows the transient read currents for UTMSG and planar, with inset illustrated the voltage program. Fig. 3(b) shows the read currents extracted at 40 ms under different read voltages after a 2 V write pulse. All UTMSG show larger transient current than planar. Besides, UTMSG with larger S would have better performance. The reason could be explained by Fig. 3(c). The insulating aluminum oxide interlayer and the resistive thin metal surrounding gate together result in a distributed resistance, leading to an RC time delay during voltage switching. During read, the electrons stored under the surrounding gate would take longer to response. Therefore, larger current could be read out, due to the edge late response. Consequently, more electrons would be delayed for larger S, and larger transient current would be expected.Fig. 4(a) and (b) show the AC signal model and the reverse-bell shape capacitance-voltage (C-V) characteristics of UTMSG, which were discussed in detail in previous work [5]. When Rsi, determined by the electron density under gate, is small enough such that the cut-off frequency 1/2πRsiCs,o is larger than the AC frequency, Cs,o could be read out. Fig. 5 shows the frequency dispersion of C-V curves. For lower frequencies, lower VG is needed for the AC signal to pass through.Fig. 6(a) shows the 10kHz C-V curves, on which ± 0.5 V voltage pulse were performed to read out two capacitance states. Fig. 6(b) shows the transient capacitance read at 0 V. When switching from + 0.5 V to 0 V, excess electron would be stored under gate initially. To balance the gate voltage, depletion region would shrink and high capacitance state would be measured, which would be more significant for UTMSG due to more delay of electron. For UTMSG at – 0.5 V and 0 V, depletion capacitance under center gate Cs,i and under total gate Cs,i + Cs,o would be read out, respectively. This means after applying a - 0.5 V pulse and then read at 0 V, UTMSG devices would experience a larger change of capacitance. Moreover, since the capacitance at - 0.5 V is lower for UTMSG with larger S, the change of capacitance would be larger. The two state capacitance windows measured at 30 ms are shown in Fig. 6(c), where larger capacitance window could be observed for UTMSG with larger S. Finally, the capacitances when sweeping voltage forwardly and backwardly and the separation between them were shown in Fig. 7(a) and (b) for UTMSG and planar devices. All UTMSG show larger separations, which further confirms the improved transient capacitance window observed in Fig. 6.In conclusion, transient behavior could be further improved by increasing the proportion of surrounding gate in UTMSG MISTD, and 17x read current and 14x capacitance window could be measured. The discovery in this work might be beneficial for the future dynamic memory design.Acknowledgement: This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and NSTC 111-2622-8-002-001[1] M. A. Green, F.D. King and J. Shewchun, Solid-State Electronics, 17, 6, pp. 551-561, (1974).[2] S.-W. Huang and J.-G. Hwu, IEEE Trans. on Electron Dev., 68, 12, pp. 6580-6585 (2022).[3] K.-H. Tseng, C -S. Liao and J. -G. Hwu, IEEE Trans. on Nanotech., 16, 6, pp. 1011-1015, (2017).[4] C.-D. Lin and J.-G. Hwu, ECS Trans., 85, 51, (2018).[5] S.-W. Huang and J.-G. Hwu, IEEE J. of the Electron Devices Soc., 9, pp. 1041-1048, (2021). Figure 1

Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)

Transient behavior of metal-insulator-semiconductor tunnel diode (MISTD) with ultra-thin metal surrounded gate (UTMSG) is discussed in this work. The influence of an important parameter, S, which is the area proportion of surrounding gate to the total gate, on the transient read current and transient capacitance window is demonstrated. Transient current is found to be larger for larger S due to more significant edge late response. By taking advantage of the unusual capacitance-voltage characteristics, improved capacitance window could be achieved. The transient current window and capacitance window of UTMSG device with S = 0.66 have been found to be 17x and 14x larger compared with planar device.

Schottky Barrier Height Modulation (SBHM) Induced Photon Current Gain in MIS(p) Tunnel Diodes for Low Operation Voltage

Schottky barrier height modulation (SBHM) mechanism is utilized on metal-insulator-semiconductor tunnel diodes (MISTD) to achieve high photon current gain. The photon current gain can reach over 24000 at 2.5 V for the MISTD with oxide thickness 3.11 nm under photon flux of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.03\times 10^{12} cm^{-2}sec^{-1}$ </tex-math></inline-formula> . The operation voltage can go down to below 1 V depending on the oxide thickness of MISTD and the requirement of the gain. For example, the MISTD with oxide thickness 2.89 nm can produce photon current gain above 2800 at 1 V under photon flux of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.03\times 10^{12} cm^{-2}sec^{-1}$ </tex-math></inline-formula> . It is found that the devices can reach an electric field in the order of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{4}-10^{5} V/cm$ </tex-math></inline-formula> under low operation voltage, which is helpful for high-speed applications. MISTD with gate metal and oxide thickness being properly chosen is simple in structure but effective in photon sensing.

Transient Current Enhancement in MIS Tunnel Diodes With Lateral Electric Field Induced by Designed High-Low Oxide Layers

In this work, the steady-state and transient behavior of the metal–insulator–semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application.

Role of Schottky Barrier Height Modulation on the Reverse Bias Current Behavior of MIS(p) Tunnel Diodes

Current and capacitance characteristics of Al/SiO2/Si(p) metal-insulator-semiconductor tunnel diode (MISTD) with oxide thickness in the range of about 2-4 nm were fabricated and studied in detail in this work. We found that the saturation reverse bias current will increase with oxide thickness in this range of oxide thickness. This non-intuitive phenomenon is caused by different levels of Schottky barrier height modulation (SBHM), which leads to the injection of the majority from metal. The majority current of Al/SiO2/Si(p) MISTD is usually neglected because of the blocking of the oxide layer and the Schottky barrier. The mechanism and numerical analysis of SBHM are discussed in this work. SBHM is significant when the oxide is thin enough for the majority to tunnel from metal to semiconductor and thick enough to hold a part of the minority inversion layer. In this specific oxide thickness range, increasing oxide thickness will increase the ability to hold the inversion layer, thus leading to higher oxide voltage (Vox) and stronger SBHM. As a result, we find that stronger SBHM lets more majority have enough energy to inject from metal to semiconductor and cause higher reverse saturation current in MISTD with thicker oxide. With the numerical analysis in our work, we also predict this non-intuitive phenomenon will start to turn around when oxide thickness is thicker than about 33Å. This phenomenon indicated that majority current is an un-neglectable component when the oxide is thick enough to hold the inversion layer partially. The analysis in this work is also helpful to complete the missing part of the theory describing the current behavior of MISTD.

Photoelectric properties of MIS structures on high-resistivity p-type silicon with aluminium nitride tunnelling insulator

Photoelectric properties of MIS tunnel diodes produced on high-resistive p-type silicon wafers with thin aluminium nitride AlN insulator layer and Pd or Al metal gate electrodes were investigated. It was found that synthesized AlN films possess a fixed positive charge, which leads to the creation of near-surface inversion layer in silicon substrate. The ratio of the photocurrent to the dark current K = Iph / Idark (on / off ratio) was found to depend on the gate electrode material, illumination intensity and the applied reverse bias. For studied MIS structures K ratio varied from 10 4 to 10 5 and was two orders of magnitude higher than that for the control MS structure without the insulator layer. High on / off ratio of such MIS structures with AlN tunnelling insulator promotes their application as an effective photodetectors in optoelectronics.

Ultra-Low Subthreshold Swing in Gated MIS(p) Tunnel Diodes With Engineered Oxide Local Thinning Layers

In this article, oxide local thinning (OLT) effects on the performance of a gated metal–insulator–semiconductor tunnel diode (MIS TD) with a p-type substrate were demonstrated through the fabrication of well-defined OLT regions at the gate and the drain. Without soft breakdown treatment of the oxide layer as reported before, the designed OLT patterns give rise to such devices to be of particular use. Specifically, sub-60 mV/decade subthreshold swing (SS) in the transfer characteristics was achieved with OLT regions at the device gate, while the operating voltage, as well as SS, could be further reduced with those at the drain. Moreover, by adjusting the number and area of OLT regions that are evenly distributed within the device, SS could be possibly optimized to a much lower value, e.g., 8.4 mV/decade, over three current decades. The enhanced lateral transport efficiency of minority carriers from the gate to the drain, which leads to the ultra-low SS, is attributed to the OLT region as an extra energy source under negative bias with its effectiveness depending on the area and thicknesses of both the relatively thick and thin oxides. The roles of these physical parameters were investigated using 2-D TCAD simulation and evidenced by experimental results.

Roles of Inner and Outer Fringe and Asymmetric Coupling Effect in Concentric Double-MIS(p) Tunneling Diodes

It has been known that the saturated current of MIS(p) tunnel diode (TD) is periphery-dependent because of magnifying of fringing-field effect [1]. Furthermore, due to its high sensitivity to the change of minority carriers from surroundings, MIS(p) shows noticeable results towards light or bias-added neighboring gate in a concentric structure [2]. Nonetheless, it is lack of discussion on the amount of coupling contribution from the inner and outer fringe of the outer ring-shaped MIS TD. In this work, two sets of ring-shaped and concentric MIS TD patterns are designed. The first set is made with the outer fringe ROo fixed and inner fringe ROi varying, and the second set is designed contrarily. The schematics of the top view, cross section and parameter table of ring-shaped and concentric double-MIS TD are shown in Fig. 1 (a) and (b), respectively. The radius of inner and outer fringe of the outer ring are named as ROi and ROo. Besides, “Vring” denotes the bias of the ring-shaped MIS TD in Fig. 1 (a) and the notation of “VI” and “VO” represent bias of inner and outer electrodes in the concentric MIS TD in Fig. 1 (b).The distinct difference lies in the saturated light current part of Fig. 2 where the result of set 1 (Fig. 2 (a)) merge perfectly while that of set 2 (Fig. 2 (b)) do not. We further divide the currents in Fig. 2 (a) with their area (JA,ring) and obtain merged currents in the accumulation region in Fig. 3 (a), indicating they are uniform TDs with same oxide thickness. Then, we divide Fig. 2 (a) with their respective total perimeter (JP,ring) and find the saturated dark currents merged better now in Fig. 3 (b). This can be attributed to the similar perimeter-dependent phenomenon as in single MIS TD case [1]. Combining the results above, it is inferred that both of the inner and outer fringes contribute to saturation current of a ring-shaped MIS TD at dark. However, with light added the dominant term in saturated current becomes that amount of charges grabbed by the outer fringe through a diverging field so that the light current shows great consistency for devices with same ROo.In the following analysis, we examine the concentric double-MIS TD structure with a 30μm gap from two operating situations. One is the case where the inner circle functions as the gate and the outer ring plays as the sensor [i.e., inner gate outer sensor (IGOS)]. In the opposite case, the inner circle serves as sensor while the outer ring works as the control gate [i.e., inner sensor outer gate (ISOG)]. It is found in our recent work [3] that the extent of the coupling effect between the inner device and the outer ring is unequal (shown in the inset of Fig. 4). By utilizing this asymmetric coupling effect, a higher sensitivity can be achieved at a lower voltage bias, therefore become more power-efficient in IGOS. Fig. 4 (a) and (b) show the I-V curves of sample A in IGOS and ISOG operations. It is observed that in the IGOS situation, the light currents under different VIG are nearly fixed. This can be interpreted as a combined result of asymmetric coupling effect and the above-mentioned inference that the main role in grabbing carriers under illumination is the outer fringe of the ring. Also, similar results are found among samples with 6 different outer ring-to-inner circle area ratios ranging from 48 to 4. Contrarily, in the ISOG situation, the extent of light current influenced by outer control bias will be relatively larger owing to the strongly besieging field.Finally, Fig. 5 shows the I-V curves of the concentric MIS TD with ROo fixed and the total power consumption of (a) IGOS and (b) ISOG operations under a control bias of 1.0V. It is noted that as the outer ring-to-inner circle area ratio increases (from ratio of C : 0.9 to A : 8), the light-to-dark current ratio rises while total power consumption becomes lower and therefore more efficient. It is concluded that the roles of inner and outer fringe are different and the coupling effect is of importance to high-density devices. This work is supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3 and MOST 107-2622-8-002-018.[1] Y. K. Lin and J. G. Hwu, IEEE TED, 61, 9, 2014[2] W. T. Hou and J. G. Hwu, ECSJ, 6, 10, 2017 [3] Y. H. Chen and J. G. Hwu, IEEE TED, 65, 11, 2018 Figure 1

Determination of border/bulk traps parameters based on (C-G-V) admittance measurements

Admittance parameters analysis can give useful information on border and bulk traps, including the traps located at the inner interface inside high-k gate stacks. The authors present a theoretical model of the high-k dielectric based MIS tunnel diode that comprises the small-signal response of the traps. The traps are charged and discharged not only by charge exchange with the substrate but also by tunnel currents between the traps and the gate electrode. The assumption of tunnel communication between the traps and the gate electrode enables arbitrary traps geometric distribution and makes the model valid not only for surface and border traps but also for the bulk ones, including traps located at the inner interface inside the gate stack. The small-signal equivalent circuit of the considered MIS structure is transformed into series (CSm, RSm) and parallel (CPm, GPm) depictions, which are commonly used in admittance measurements (C-G-V). The comparison between simulation results and measurement data may be used to determine the trap parameters in the investigated device as it is presented in the paper.

Roles of Inner and Outer Fringe and Asymmetric Coupling Effect in Concentric Double-MIS(p) Tunneling Diodes

During the studies of coupling effects between the outer ring and inner circle in a concentric structure of double-metal-insulator-semiconductor tunnel diode, we have proposed an asymmetric coupling effect to account for the distinctive difference between two opposite operations. However, further investigation is needed to make our mechanism more robust. In this work, we designed two sets of ring-shaped and concentric MIS tunnel diode lithographic patterns with a fixed inner fringe in the first set and a fixed outer fringe in the second set. From both the experimental and TCAD-simulated results, we have found that the major role in grabbing charges is the outer fringe of a ring-shaped MIS structure and that this outer fringe-dominated characteristic accompanied with the asymmetric coupling effect results in the observable difference in two contrary operation modes where the inner circle and outer ring take turns to play as the control gate.

On/Off Current Ratio Enhancement By Reducing Electrode Separation in Gate-Controlled MIS Tunnel Transistor

Saturation current of a MIS (p) tunnel diode is strongly dependent on the Schottky barrier height. It was found a gate MOS capacitor near an MIS tunnel diode may affect the saturation current of the tunnel diode. It was supposed that the increase of electron diffusion from a gate MOS capacitor will cause the decrease of the Schottky barrier height and lead to the increase of saturation current [1]. Furthermore, transistor characteristic of this structure was also proposed [2]. By varying gate bias, electron diffusion current varies as well. Since two current states of the tunnel diode occurs, this device can be considered as a transistor. In this work, different gap distances between gate and MIS tunnel diode were studied. It was found that a smaller gap distance may lead to a stronger couple effect. Hence, reduction of gap distance can both enhance tunnel diode saturation current and the Ion / Ioff ratio of the gate-controlled MIS tunnel transistor. The schematic top view and cross section of the gate-controlled MIS tunnel transistor is shown in Fig. 1. We named the inner MIS tunnel diode drain and the outer ring gate. The radius of the inner circle, R1, is 85μm. The gap distance, S, is varying from 5μm to 25μm. The radius of the outer ring, R2, is (585+S)μm. Fig. 2(a) shows ID versus VD with gate floating. The sample without gate structure is denoted as no ring. It can be regard as the gap distance is infinity. Fig. 2(b) shows the saturation current ID,sat versus gap distance of two different oxide thickness. We found that the saturation current increases as the gap distance reduces. Fig. 2(c) and (d) shows the schematic of the mechanism, which can be explained by couple effect. When the gap distance reduces, couple effect becomes stronger, and the electron diffusion from gate’s inversion layer to drain increases, which leads to a larger drain saturation current. Fig. 3(a) shows the ID-VG of the gate-controlled MIS tunnel transistor for different gap distances and VDS’s. It was shown that there are on state and off state for ID. For the on state, the gate bias voltage is around 0V, and the gate MOS capacitor is in inversion region, which introduces a large number of electron to couple to drain. We found that when VDS is smaller than Vsat, ID are irregular because ID do not saturate so it do not follow the rule as observed in Fig. 2(b). However, when VDS is larger than Vsat, drain current becomes ID,sat and increases with the reduction of gap distance. For the off state, gate bias is near VFB, the gate MOS capacitor is close to accumulation region. In this situation, the electron concentration underneath gate is less than the electron concentration in bulk np0. Only a little electron diffusion from the gap region to drain, and leads to a quite low ID. The off current is therefore decreases as the gap distance reduces. Fig. 3(b) shows the schematic of the mechanism. When the gap distance becomes smaller, the electron concentration of the gap region decreases due to the stronger couple impact of the gate MOS capacitor, and leads to the decrement of ID. We called this phenomenon as strong couple effect. Fig. 3(c) and (d) show Ion and Ioff versus gap distance and the Ion / Ioff ratio of drain current of different oxide thickness. It is found that for the smaller gap distance, we got smaller Ioff and larger Ion, and therefore a larger Ion / Ioff ratio of the gate-controlled MIS tunnel transistor. Moreover, in Fig.3(c), it was found that when oxide thickness increases, Ion increases and Ioff decreases, so a larger Ion / Ioff ratio can be obtained. For a gate-controlled MIS tunnel transistor, we use the bias of gate to control the drain MIS tunnel diode by couple effect. In this work, we found that reduction of gap distance can enhance the couple effect of on state and enhance strong couple effect to reduce the off state current. A large Ion / Ioff can be expected. In conclusion, the design of proper small gap distance is the way to improve the performance of a gate-controlled MIS tunnel transistor. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. Most 105-2221-E-002-180-MY3 and 106-2221-E-002-196-MY3. [1] C. S. Liao and J. G. Hwu, ECS Trans., 75(5), 77 (2016) [2] C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, 62, 2061 (2015) Figure 1

Photo Sensitivity Enhanced By the Modulation of Oxide Thickness in MIS(p) Structure

It was found that the ratio of light to dark current can be enhanced by coupling effect with simple MIS(p) on concentric MIS structure [1]. Gate with bias can largely decrease dark current, and thereby improve the ratio. In this work, to research deeper about it, the enhancement of ratio with gate voltage is concentrated on the modulation of oxide thickness. The topside and cross section of the studied MIS(p) structure with the concentric pattern is shown in Fig. 1(a). The radius of inner circle r1 is 85um. The space between inner and outer gate, i.e., s, is 20um. The outer radius of the ring is 300um. Here, the inner circle is defined as diode and the outer ring is defined as gate. Also, according to the previous work [1], a specific gate voltage of VX is defined as when it causes the lowest diode dark current in ID-VG curve (the inset in Fig. 1(b)) and therefore exhibits the largest enhanced ratio. Fig. 1(b) a shows I-V curve of light current and dark current with VG=VX in two oxide thickness of 2.5nm and 3nm. The ratio is defined by the light current to dark current at 2.5V which is located at the diode current saturation region. Comparing the ratio of light to dark current in two thickness, it is obvious to show that the ratio is dependent on oxide thickness and MIS structure with a thicker oxide might have a higher ratio. To further study the relation of ratio and thickness, samples with different thickness were explored to examine their light to dark current ratios as shown in Fig. 2(a). From Fig. 2(a), it obviously shows that the ratio is highly increased for thicker oxide. Also, in order to see the effect of illumination, three strength of illumination with 131lux, 306lux, and 410lux were studied. Fig. 2(b) shows that thicker oxide indeed has a higher ratio than thinner counterpart no matter what the strength of illumination is. To analyze the dependency of the saturation current on oxide thickness, the dark current, light current and the ratio of light to dark current are separately presented for various thicknesses as shown in Fig. 3(a). It’s clear to indicate that the dark current reduces with the oxide thickness and light current has no obvious relation with thickness. Hence, the discussion is divided into two parts. To discuss about dark current, Fig. 3(b) demonstrates of the carrier and two currents part of dark diode current from the gate region under VG=VX in dark environment. Because gate voltage is biased in the minimum diode current which is near VFB, minority carrier gathered under gate region is very few. Then, the diffusion current from gate to diode is very small due to the subtle divergence of carrier concentration. Therefore, the diffusion current by coupling effect is largely reduced and contributed less to the barrier height modulation of diode. As a result, diode current is mainly dominated by the injection current part from the gate region. In Fig. 3(c), because the gate current which induces the injection current is strongly dependent on oxide thickness, it implies that thicker sample which has lower injection current has lower saturation current. It confirms that dark current is clearly decreased with increasing thickness under VG=VX in Fig. 3(a). For the light current part, because the light current is also contributed from light-induced electron-hole pairs, the light current is not solely dependent on oxide thickness. Hence, light current does not show similar dependence of thickness. The ratio of light to dark current is largely enhanced by the largely decrease of dark current due to the increase of oxide thickness. Furthermore, the ratio of light to dark current increases with the stronger strength of illumination in the thicker MIS sensor as shown in Fig. 2(b). The result indicates that there is a larger light current in the stronger illumination because of more electron-hole pairs. Therefore, the ratio of light to dark current is increased with the strength of illumination. In conclusion, the modulation of oxide thickness is of importance to the photo sensitivity of MIS(p) tunnel diode. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3 and MOST 106-2221-E-002-196-MY3. [1] W.T. Hou and J.G.Hwu*, 2017, “Photo Response Enhancement in MIS(p) Tunnel Diode via Coupling Effect by Controlling Neighboring Device Inversion Level”. Electronic and Photonic Devices and Systems, ECS Journal of Solid State Science and Technology, 6(10), pp. Q143-147, 2017 Figure 1

Tunable Negative Differential Resistance in MISIM Tunnel Diodes Structure With Concentric Circular Electrodes Controlled by Designed Substrate Bias

The tunable negative differential resistance (NDR) characteristics of metal–insulator–semiconductor–insulator–metal (MISIM) tunnel diodes (TDs) structure with thin oxide were observed by biasing the substrate simultaneously with one of the TDs under designed voltage drops ( $\Delta \text{V}$ ). An inner circular electrode TD surrounded by a ring-shape electrode TD gate pattern was adopted. The NDR region can be adjusted by varying the $\Delta \text{V}$ between the inner TD and the body. Not only the peak-to-valley current ratio (PVCR) but also the voltage range where NDR occurs can be controlled. It is supposed that the injected electrons and the inversion charges increase and decrease with negative bias, respectively, for the MIS(p) TD and play an important role in this observation. Meanwhile, the asymmetry of inner gate and ring gate enhances the coupling efficiency at reverse bias region. In this paper, the PVCR can be tuned to more than two orders and the voltage of the NDR region can be shifted to larger than 1 V. The tunable NDR characteristic of MISIM provides a possible application of MIS TD.

MIS(p) Saturation Tunneling Current Controlled by Neighboring MIS Inversion Level Via Coupling Effect

To study the current coupling effect, novel neighboring MIS tunnel diodes were fabricated and examined. It is found that the saturation dark or light current of MIS tunnel diode can be elevated with more neighboring floating MIS structures, resulting from the lateral diffusion. And coupling also makes saturation current of those neighboring structures the same despite their various sizes. An irradiance of 6 mW/cm2 and gradually-minimizing distance both give rise to the greater saturation current for central MIS diode. TCAD simulation also shows the existence of lateral diffusion; furthermore, the fringing field would increase the efficacy of drift current under nano-scale distance among devices.

Rearrangement of Fringing Field by Sidewall Passivated Metal Gate in MIS Tunnel Diode

In order to reduce the interference caused by fringing field, a cost-effective method to form passivation layer on the edge side of aluminum gate was demonstrated. In capacitance voltage (C-V) characteristics, it is found that the initiation point of deep depletion is at a smaller VG, the sensitivity to light is less evident, and the value of capacitance is more area dependent. All of these significant different observations are indications of the rearrangement of fringing field. Furthermore, TCAD simulations were employed to support the observed phenomenon.

Enhancement of Light-to-Dark Current Ratio Via Coupling Effect for MIS (p) Tunnel Diode Photo Sensors

MIS tunnel diodes have been used as sensing devices since MIS tunnel currents are very sensitive to surrounding signals. It is found that MIS tunnel currents are perimeter-dependent due to magnifying of finging-field effect. And, it is shown that MIS saturation currents have a strong relationship with Schottky barrier height which indicates that a slight change of Schottky barrier height would make a big move of MIS tunnel currents. In this work, a structure of concentric circle is used. Photo response is examined by light-to-dark current ratio Ilight/Idark. It is found that MIS tunnel currents can be controlled by the voltage bias of the nearby MOS capacitor since the voltage bias of the nearby MOS capacitor(VG) determines the amount of minority carriers underneath the gate and therefore the diffusion currents to the MIS sensing tunnel diode. As a result, by well controlling VG, Ilight/Idark ratio can be effectively enhanced. It is also shown that under different intensities of illumination, the maximum of Ilight/Idark occurred at different value of VG. The underlying mechanism will be explained later. Fig.1(a),(b) show the top and schematic view of the concentric circle device with radius of inner ring R1=170um, and outer ring R2=675um. Fig.2 shows the MIS tunnel currents ITD versus VTD with VG floating. It is found there are different mechanisms dominating when VTD is biased at negative and positive voltage. When VTD is biased at negative voltage, ITD increases with oxide thickness decreasing. This can be explained by gate-injection theory. However, when VTD is biased at positive voltage, ITD increases with oxide thickness increasing. This can be explained by Schottky barrier theory, that is when oxide thickness increases, the voltage drop on the oxide will increase so the Schottky barrier height will decrease causing the increase of the tunnel current ITDshown in Fig.2. Fig.3(a) shows the MIS tunnel currents ITD of different oxide thicknesses at dark and with light versus VTD with VG floating. Solid line and dash line represent the dark current and light current respectively. Note that the illumination intensity is 7mW/cm2.Three different oxide thicknesses were extracted out. Fig.3(b) shows the Ilight/Idark versus VTD with VG floating. From the figure, it is shown that the Ilight/Idark is of one order. Fig.3(c) shows the MIS tunnel currents ITD of different oxide thicknesses at dark and with light versus VG while VTD fixed at 2.5V. Fig.3(d) shows the Ilight/Idark versus VG with VTD fixed at 2.5V. Surprisingly, it is found that when VG is biased around -0.5V, Ilight/Idark can be enhanced to two orders. The underlying mechanism is that when VG is biased near the flat-band, there are nearly no charges underneath the gate, so there are few charges accumulating underneath the tunnel diode causing the low tunnel current and hence the enhancement of Ilight/Idarkratio. In the following, the intensity of light was enhanced to 15mW/cm2. Fig.4(a) shows the MIS tunnel currents ITD of different oxide thicknesses at dark and with light versus VTD with VG floating. Also, three different oxide thicknesses were extracted out. Fig.4(b) shows the corresponding Ilight/Idark versus VTD with VG floating. It is shown that the Ilight/Idark is of two orders. Fig.4(c) shows the MIS tunnel currents ITD of different oxide thicknesses at dark and with light versus VG while VTD fixed at 2.5V. Fig. 4(d) shows the Ilight/Idark versus VG with VTD fixed at 2.5V. Amazingly, it is found that when VG is biased near -0.9V, the Ilight/Idarkratio can be effectively enhanced to four orders. What’s interesting is that the maximum of Ilight/Idark ratio occurred at different value of VG compared to the light intensity is 7mW/cm2. The reason is that when implementing weak illumination which is 7mW/cm2, the number of light-induced carriers is relatively low which means the tunnel currents are still affected by the charges from the gate. As a result, it can be inferred that light currents change relatively high while sweeping VG. However, when implementing stronger illumination which is 15 mW/cm2, the number of light-induced carriers will increase, so the coupling effect from the gate will reduce causing light currents move relatively slightly while sweeping VG. Consequently, the maximum of Ilight/Idarkratio will occur at where the dark currents is lowest. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. Most 105-2221-E-002-180-MY3 and NTU-ERP-105R89081 [1] C. S. Liao and J. G. Hwu, ECS Trans., 75, 77 (2016). [2] W.C. Kao and J.G Hwu, ECS Trans., 72(2), 223 (2016) Figure 1

Rearrangement of Fringing Field by Sidewall Passivated Metal Gate in MIS Tunnel Diode

It is known that the dielectric constant (ϵ value) of Al2O3 is larger than SiO2. Based on the equation Ｑ= ϵＥ, it is predicted that it is more difficult for electric field to pass through Al2O3 passivated layer with respect to SiO2. A method to rearrange and block fringing field in MIS tunnel diode was demonstrated. After the gate electrodes were defined and patterned by lithography and wet etching, the photoresist on the top of aluminum gate was retained. And then, the sample was immersed in nitric acid solution by the mixture of nitric acid and water in a ratio of 2:1. After partial nitric acid oxidation for 2 mins, the aluminum oxide layer was formed on the edge side of aluminum gate. There are two batches of MIS tunnel diodes, which are denoted by MIS and Al2O3SP-MIS. The cross-section of these two devices is shown in Fig. 1. For previous study [1-2], the deep depletion behavior could be described with several periods. Initially, the minority carriers could balance the gate bias in weak inversion, so the capacitance would hold for a period. If the amount of minority carrier is sufficient, the value of capacitance will rise. Subsequently, when a larger bias is applied, the edge region due to fringing field would make the device enter into deep depletion at edges while the bulk region is still in depletion. At this moment, the minority carrier would leak from substrate to gate, so the value of capacitance would drops rapidly. Therefore, the arch would appear in C-V curve. Finally, both the edge and the bulk regions would enter into deep depletion, and the value of capacitance drop continually. From Fig. 2(a), it is found that the arch of Al2O3SP-MIS is in front of the arch of MIS. It is implied that Al2O3SP-MIS enters into deep depletion much quickly. For Al2O3SP-MIS, fringing field at the edge of gate electrode is stronger, so it would make the device enter into deep depletion earlier. However, the arch of Al2O3SP-MIS is higher than MIS, and Al2O3SP-MIS has higher capacitance values than those of MIS. It means that there are more carriers under the gate electrode for Al2O3SP-MIS. The TCAD simulation in Fig. 3 confirms this experimental result. Under weak inversion, the carrier is more concentrative in Al2O3SP-MIS, so more carriers could response to the gate bias. In order to generate more hole and electron carriers, incandescent light was applied. From Fig. 2(b), it is also found that the arch of Al2O3SP-MIS is in front of the arch of MIS. In contrast to w/o light, the arch of MIS is higher than Al2O3SP-MIS. Because fringing field in MIS extends more distance away than Al2O3SP-MIS, so MIS would seize more carriers which were generated by incandescent light. Fig. 2(c) shows that the difference between w/o light and w/ light for Al2O3SP-MIS is less evident since fringing field seizes fewer carriers under incandescent light. It is further confirmed that fringing field was blocked by Al2O3passivated layer. In order to confirm the experimental results, TCAD simulations were employed to discuss the rearrangement of fringing field. Fig. 4 shows the magnitude of electric field extracted from TCAD simulations. It is observed that there are two peak values in Al2O3SP-MIS while MIS only one. The first peak of Al2O3SP-MIS is lower than MIS, which implies that fringing field is reduced by Al2O3 passivated layer. The second peak of Al2O3SP-MIS is higher than MIS, which means that fringing field would be enhanced at the edge of gate electrode, so it would seize more minority carrier to leakage from substrate to gate and make the device enter into deep depletion earlier. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 103-2221-E-002-252-MY3 and MOST 105-2622-8-002-001.