Minimum-length Test Sequences Research Articles

Test sequence construction from SFC specification

This paper focuses on conformance test of electronic programmable devices whose specification is given in Sequential Function Chart (SFC). More precisely, a method is proposed to obtain automatically, from this specification, one minimum length test sequence which permits the exhaustive test of the behavior of the device. This method takes advantage of previous results on construction of the state machine representation of a SFC and on test of Mealy machines; conversely, it extends the industrial use possibilities of this latter technique. The contribution is exemplified on a simple model.

Distributed testing without encountering controllability and observability problems

The objective of testing is to determine whether a system under test conforms to its specification. In distributed test architectures that utilize remote testers, this objective can be complicated by the fact that testers may encounter problems relating to controllability and observability during the application of a test sequence. Existing solutions to these problems involve first constructing a test sequence from the specification of an implementation under test, and then inserting coordination messages or appending selected test subsequences that prevent the occurrences of controllability and observability problems during the application of the resulting test sequence. This paper proposes a method that utilizes a set of transformation rules to construct an auxiliary directed graph from a given specification, and constructs a rural Chinese postman tour in this graph to yield a minimum-length test sequence where there is no potential controllability or observability problems, and where the use of coordination messages is minimized.

A matroid-theoretic solution to an assignment problem in the conformance testing of communication protocols

The minimum length test sequence generation method proposed previously (1988) for conformance testing of a protocol uses Unique Input Sequences (UIS) for state identification. This method, called the U-method, requires that the test graph, a graph derived from the protocol, be connected. This requirement also needs to be satisfied in the case of the MU-method, which assumes that the multiple UISs are available for each state. Thus, the U-method and the MU-method may not provide minimum length test sequences in cases where the test graph is not connected. Nevertheless, these methods generate minimum length test sequences with high fault coverage whenever the test graph is connected. This raises an important problem: Does there exist an assignment of UISs to the transitions such that the resulting test graph is connected? In this paper, we formulate this problem as a maximum cardinality two matroid intersection problem and discuss an efficient algorithmic solution. We also point out the role of the work in the minimum length test sequence generation problem.

Testing protocols modeled as FSMs with timing parameters

An optimization method is introduced for generating minimum-length test sequences taking into account timing constraints for FSM models of communication protocols. Due to active timers in many of today's protocols, the number of consecutive self-loops that can be traversed in a given state before a timeout occurs is limited. A test sequence that does not consider timing constraints will likely be unrealizable in a test laboratory, thereby potentially resulting in the incorrect failing of valid implementations (or, vice versa). The solution uses a series of augmentations for a protocol's directed graph representation. The resulting test sequence is proven to be of minimum-length while not exceeding the tolerable limit of consecutive self-loops at each state. Although UIO sequences are used for state verification method, the results also are applicable to test generation that uses distinguishing or characterizing sequences.

Testability analysis and behavioral testing of the Hopfield neural paradigm

Testability analysis and test pattern generation for neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of Hopfield's networks, as the simplest example of networks with feedback loops. A behavioral error model based on finite-state machines (FSM's) is introduced. Conditions for controllability, observability and global testability are derived to verify errors excitation and propagation to outputs. The proposed behavioral test pattern generator creates the minimum length test sequence for any digital implementation.

Dual-state augmentation for minimizing conformance test costs

This paper discusses the dual-state augmentation method to generate the minimum-length test sequences using the multiple UIO sequences of minimal and nonminimal lengths. In dual-state augmentation, all UIO sequences (minimum-length or not) can be used to minimize the test sequence length. The resulting test sequences are significantly shorter than the test sequences generated by the existing methods which only use the minimum-length UIO sequences. As a case study, the dual-state augmentation technique is applied to a subset of the ISDN Network Layer protocol for supplementary voice services. Significant savings on test sequence length are observed.

Test embedding with discrete logarithms

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >

Testing Memories for Single-Cell Pattern-Sensitive Faults

The design of minimum-length test sequences for pattern sensitivity in random-access memory (RAM) arrays is examined. The single pattern-sensitive fault (SPSF) model is used in which operations addressed to at most one memory cell are allowed to be faulty at any time. The influence of an SPSF affecting cell Ci is restricted to a fixed set of cells called the neighborhood of Ci. A new method is presented for efficiently generating the sequence of writes required in an SPSF test. This method yields optimal sequences for a useful class of neighborhoods called tiling neighborhoods. It is observed that RAM neighborhoods can be interpreted as polyominoes. A general procedure is given for constructing an SPSF test containing the minimum number of writes but a nonminimum number of reads. The difficult problem of minimizing the number of reads in an SPSF test is investigated for the 2-cell memory M2. A test of length 36 for M2 is derived which is optimal under certain reasonable restrictions. It is demonstrated that minimum-length SPSF tests can be inherently asymmetric.