Minimum Area Layout Research Articles

Penentuan Titik Lokasi Pelabuhan Penyeberangan Amed Di Kabupaten Karangasem

Accumulation of social activity, economy and transportation that occur in Southern part of Bali adversely affects at transportation infrastructure carrying activity in this area. These require the government to get the solution of this problem. Through spatial planning area of Bali province 2005, governments establish Amed Bay developed as crossing harbor. These cases mean to divide the shout hem traffic line and support the development in northern part of Bali. The object of this research is in Purwakerti village, district of Abang, Karangasem regency. Research held based on technical and legality review. In advance analyze of those aspects that established some alterative potential location based on area requirement and mapping survey result. Following, each location alternative disassembly and examined their advantages and disadvantages in each aspect. Technical aspect analyze of land and territorial water technique. The approach that used in harbor location selection for this technique is weighting and assessment method in assessment matrix. The weighting value that used refers to harbor location selection in Makian bay. Meanwhile, for legality aspect, analyzed by policy review that relate to spatial area and location selection of harbor development. Based on minimum area demand analyze that 0.7 Ha for land facilities and 15.8 Ha for waters facilities. Refers to minimum area demand and layout spatial survey, four locations are selected for alternative points. After technical and legality aspect analyzed, then obtained second area chosen which located in Amed country, Purwakerti village.

A layout adjustment problem for disjoint rectangles preserving orthogonal order

AbstractThis study considers a set of n rectangles arranged on a plane, and, in particular, the problem of modifying the initial layout within a minimum area while meeting certain conditions, namely, preservation of orthogonal order and prevention of intersection between rectangles. A heuristic algorithm for this problem with O(n2) complexity was proposed by Misue and colleagues. First, the problem of minimum‐area layout adjustment is shown to be NP‐complete. Then, another heuristic algorithm is examined that results in smaller layout area than that of Misue and colleagues. Using computational experiments with random initial layouts, the proposed algorithm is proven to require 15 to 20% of the area required by the Misue algorithm, especially with a large number of rectangles. © 2002 Scripta Technica, Syst Comp Jpn, 33(2): 31–42, 2002

On the approximability of two tree drawing conventions

We consider two aesthetic criteria for the visualization of rooted trees: inclusion and tip-over. Finding the minimum area layout according to either of these two standards is an NP-hard task, even when we restrict ourselves to binary trees. We provide a fully polynomial time approximation scheme for this problem. This result applies to any tree for tip-over layouts and to bounded degree trees in the case of the inclusion convention. We also prove that such restriction is necessary since, for unbounded degree trees, the inclusion problem is strongly NP-hard. Hence, neither a fully polynomial time approximation scheme nor a pseudopolynomial time algorithm exists, unless P=NP. Our technique, combined with the parallel algorithm by Metaxas et al. [Comput. Geom. 9 (1998) 145–158], also yields an NC fully parallel approximation scheme. This latter result holds for inclusion of binary trees and for the slicing floorplanning problem. Although this problem is in P, it is unknown whether it belongs to NC or not. All the above results also apply to other size functions of the drawing (e.g., the perimeter).

Faster Approximation Algorithms For the Unit Capacity Concurrent Flow Problem with Applications to Routing and Finding Sparse Cuts

This paper describes new algorithms for approximately solving the concurrent multicommodity flow problem with uniform capacities. These algorithms are much faster than algorithms discovered previously. Besides being an important problem in its own right, the uniform-capacity concurrent flow problem has many interesting applications. Leighton and Rao used uniform-capacity concurrent flow to find an approximately “sparsest cut” in a graph and thereby approximately solve a wide variety of graph problems, including minimum feedback arc set, minimum cut linear arrangement, and minimum area layout. However, their method appeared to be impractical as it required solving a large linear program. This paper shows that their method might be practical by giving an $O(m^2 \log m)$ expected-time randomized algorithm for their concurrent flow problem on an m-edge graph. Raghavan and Thompson used uniform-capacity concurrent flow to solve approximately a channel width minimization problem in very large scale integration. An $O(k^{{3 / 2}} (m + n\log n)$ expected-time randomized algorithm and an $O(k\min \{ n,k\} (m + n\log n)\log k)$ deterministic algorithm is given for this problem when the channel width is $\Omega (\log n)$, where k denotes the number of wires to be routed in an n-node, m-edge network.

Minimum area layout of series-parallel transistor networks is NP-hard

Functional cells are a physical realization of complex MOS gates. Efficient algorithms for minimizing the width of a functional cell are known. Every solution to the width minimization problem leads to a cell of a certain height. It is shown that, even for functional cells of complex MOS gates represented by series-parallel transistor networks, the problem of finding a solution of minimum width that also minimizes the height is NP-hard. >

A PARALLEL ALGORITHM FOR MINIMUM DUAL-COVER WITH APPLICATION TO CMOS LAYOUT

In a pair of planar graphs (G, Gd), with Gd being the dual graph of G, a sequence of distinct edges is a dual-Euler trail if it is a trail both in G and in Gd. A set of disjoint dual-Euler trails that simultaneously cover G and Gd is called a dual-cover. We present an O( log n) time and O(n) processors algorithm, in PRAM model, based on the graph separator theory, for obtaining a minimum cardinality dual-cover in a pair of series-parallel graphs (G, Gd), where n is the total number of edges. We employ the proposed algorithm to obtain a minimum-area VLSI layout of CMOS functional cells. Our algorithm, when implemented in a serial environment performs better than previous algorithms and produces more compact layouts.

Layout optimization of static CMOS functional cells

A general theory for designing minimum-area layouts of static series-parallel CMOS functional cells (also called complex gates) in a standard cell layout style is presented. T. Uehara and W.M. vanCleemput. (1981) originally formulated this as the graph optimization problem of finding the minimum number of dual trails that cover a multigraph model of M of a cell. The present theory provides a formalism for the analysis of series-parallel graphs and identifies the mathematical structures that underlie the layout problem. It also leads to two efficient algorithms for designing minimum area functional cell layouts. The first algorithm, TrailTrace, accepts an ordering of M that is fixed, typically for performance reasons, and produces the minimum area layout for that ordering. Its time complexity is linear in the number of transistors in the cell. The second algorithm, R-TrailTrace, reorders M and produces the best layout area that can be achieved for any reordering that preserves the cell's functionality.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digraph Relaxation for 2-Dimensional Placement of IC Blocks

A new graph-theoretic representation of the placement of rectangular IC blocks of arbitrary size and aspect ratio is proposed. This representation, called a relaxed digraph, provides an efficient model for two-dimensional calculations of minimum area layouts. Unlike other digraph models, the structure of the relaxed digraph represents an entire class of layout configurations derivable from a given initial placement of blocks. This model, therefore, provides greater flexibility in block placement than can be obtained from stiff digraph representations. A necessary and sufficient condition is derived for the existence of a nonoverlapping arrangement of rectangular cells in terms of the relaxed digraph representation. Based on this result, a fixed digraph representation can be selected from the relaxed digraphs that minimizes the layout area. The minimization utilizes positional constraints imposed by the relaxed digraphs and estimated routing space requirements. The area minimization is formulated as a quadratic optimization problem and solved using mathematical programming methods. The resulting modified digraph can then be used as a graph model for further calculations of a minimum area and routing-feasible layout.