Minimum Silicon Area Research Articles

Real-Time Compact Digital Processing Chain for the Detection and Sorting of Neural Spikes from Implanted Microelectrode Arrays

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm2/ch, 7.16 μW/ch, 0.0168 mm2/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively.

Phase noise optimization of integrated ring voltage-controlled oscillators by metaheuristics

<abstract><p>Real applications of integrated circuits (ICs) require satisfying strong target specifications, which challenge is focused on trading off specifications that are in conflict, i.e. improving one characteristic can degrade other(s). This is the case of designing a ring voltage-controlled oscillator (VCO) using IC nanometer technology, with the goal to accomplish a wide frequency and voltage-control tuning range, low silicon area, among others. For real ring VCO applications, an open challenge is guaranteeing minimum phase noise, which is in conflict with main dynamical characteristics when maximizing frequency range, voltage-control range, gain, and minimizing silicon area and power consumption. To cope with these design problems, we show the minimization of the phase noise of a ring VCO applying two metaheuristics, namely: Differential evolution (DE) and particle swarm optimization (PSO), which have the ability to handle constraints that are relevant to generate optimal solutions. The results show that both DE and PSO are effective in the optimization of the ring VCO. The comparison of the best phase noise results obtained with DE (-129.01 dBc/Hz @1MHz) and PSO (-124.67 dBc/Hz @1MHz) algorithms, not only show that the DE solution being lower by 4.34 dBc/Hz with respect to the best solution provided by PSO, but also it is quite satisfactory in contrast to similar works. Finally, the optimized ring VCO characteristics are compared herein with several designs considering a figure of merit, gain, frequency and voltage-control ranges.</p></abstract>

Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency

Crossbar-based neuromorphic chips promise improved energy efficiency for spiking neural networks (SNNs), but suffer from the limited fan-in/fan-out constraints and resource mapping inefficiency. In this paper, we propose a new hardware mechanism to enable configurable combination of cores, called coreset. Using this hierarchical method, our end-to-end CSM (which stands for the ‘CoreSet Method’) framework efficiently solves the fan-in/fan-out issues and significantly improves the resource efficiency. Experiment results show that CSM can efficiently support complex network structures as well as significantly improving accuracies. Up to 4.6% improvement compared with those achieved by other neuromorphic chips (i.e. IBM TrueNorth and Intel Loihi), on the CIFAR-10, CIFAR-100 and SVHN datasets is achieved, matching the accuracies of state-of-the-art SNN models. In addition, compared with IBM TrueNorth, CSM achieves improvements of up to 18.5×,6.04× and 3.33× in memory efficiency, core efficiency and extrapolated throughput, respectively, thus enabling support for large-scale modern networks (such as VGG). In fact, our method can find optimal core sizes for minimal silicon area. As a proof of concept, we have implemented an FPGA emulation of coreset-supported neuromorphic computing. It achieves up to 7,737× speed-up compared to software simulation, thus not only facilitating SNN structure exploration and verification in a timely manner, but also enabling earlier prototyping for better neuromorphic hardware performance investigation.

Ultrafast Large-Scale Chemical Sensing With CMOS ISFETs: A Level-Crossing Time-Domain Approach.

The introduction of large-scale chemical sensing systems in CMOS which integrate millions of ISFET sensors have allowed applications such as DNA sequencing and fine-pixel chemical imaging systems to be realised. Using CMOS ISFETs provides advantages of digitisation directly at the sensor as well as correcting for non-linearity in its response. However, for this to be beneficial and scale, the readout circuits need to have the minimum possible footprint and power consumption. Within this context, this paper analyses an ISFET based pH-to-time readout using an inverter in the time-domain as a level-crossing detector and presents a 32×32 array with in-pixel digitisation for pH sensing. The inverter-based sensing pixel, controlled by a triangular waveform, converts the pH response into a time-domain signal whilst also compensating for sensor offset and thus resulting in an increase in dynamic range. The sensor pixels interface to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast asynchronous conversion whilst using minimal silicon area. Parallel outputs of 32 TDC interfaces are serialised to achieve fast data throughput. This system is implemented in a standard 0.18 μm CMOS technology, with a pixel size of 26 μm × 26 μm and a TDC area of 26 μm×180 μm. Additionally, we investigate the use of additional offset compensation by having half of the array implemented with the floating gate tied down via a well diode. Measured results demonstrate the system is able to sense reliably with an average pH sensitivity of 30mV/pH, whilst being able to compensate for sensor offset by up to ±7V. A resolution of 0.013pH is achieved and noise measurements show an integrated noise of 0.08pH within 2-500Hz and SFDR of 42.6dB. The total power consumption of the system is measured to be 11.286mW when operating at a high frame rate of 1KFPS.

Embedded Deterministic Test Points

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of $2\times $ – $4\times $ compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are $\alpha$ and $\beta$ recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing. In this brief, a novel relation existing between the $\alpha$ and $\beta$ metrics is introduced, leading to a novel add–compare–select (ACS) architecture. The proposed technique can be applied to both the precise approximation of log-MAP and max-log-MAP ACS architectures. The proposed ACS design, which is implemented in a 0.13- $\mu\mbox{m} $ CMOS technology and customized for the LTE standard, results in, at most, 18.1% less area compared with the reported designs to date while maintaining the same throughput level.

An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098mm2. The converter, designed in GPDK 90nm CMOS, exhibits maximum sampling frequency of 100kHz & consumes 6.75µW at 1V supply. Calculated signal to noise and distortion ratio (SNDR) at 1V supply and 100kS/s is 48.68dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×1020, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer specification and achieves -91 dBm and -96 dBm sensitivity at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> BER for π/4-DQPSK and π/2-DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~ 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.

A 1.8-V operation Analog CMOS Baseband for Direct Conversion Receiver of IEEE 802.11a

This paper describes a CMOS analog baseband circuits for direct-conversion receiver of5GHz IEEE 802.11a. The analog baseband consists of I/Q signal paths which have channel selection filter, programmable gain amplifier (PGA). An active-RC channel selection filter for WLAN is described whose cut-off frequency is tunable from 6MHz to 20MHz. This frequency tuning range is sufficient to cover IEEE802.11a (20MHz) including the effect of process, voltage, temperature variations. For wide tuning range, a differential R-2R ladder has been developed which gives widely variable resistance with minimum silicon area. Wide bandwidth operational amplifier (op-amp) is designed to dissipate small power by employing a current re-using feed forward frequency compensation scheme. For high linearity, the PGA is constructed with op-amp and resistor based inverting amplifiers. For minimum power consumption, the op-amps employ the current re-using feedforward frequency compensation. The input third-order intercept point (iIP3) is 20dBV at the highest gain mode. The input referred noise is 13 √ at the lowest gain mode. Implemented in a 0.18 m CMOS technology, the gain of the programmable gain amplifier (PGA) can be controlled from 2.5dB to 52.5dB with 0.5dB step.

On the design of power- and area-efficient Dickson charge pump circuits

This paper aims at investigating some methods for designing an area- and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top- and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1---2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this connection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.

Convergence analysis of an online approach to parameter estimation problems based on binary observations

In this paper, we present an online identification method to the problem of parameter estimation from binary observations. A recursive identification algorithm with low-storage requirements and computational complexity is derived. We prove the convergence of this method provided that the input signal satisfies a strong mixing property. Some simulation results are then given in order to illustrate the properties of this method under various scenarios. This method is appealing in the context of micro-electronic devices since it only requires a 1-bit analog-to-digital converter, with low power consumption and minimal silicon area.

An implantable electrical stimulator for phrenic nerve stimulation

Phrenic nerve stimulation is a technique whereby a nerve stimulator provides electrical stimulation of the phrenic nerve to cause diaphragmatic contraction in patients with respiratory failure due to cervical spinal cord injury. This paper presents an eigth-channel stimulator circuit with an output stage (electrode driving circuit) that doesn’t need off-chip blocking-capacitors and is used for phrenic nerve stimulation. This stimulator circuit utilizes only 1 output stage for 8 channels. The proposed current generator circuit in this stimulator reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption. An 8 bit implementation is utilized for this current generator circuit. The average pulse width for this eight- channel stimulator with 1 mA current, 20 Hz frequency and 8 bits resolution, is 150 - 300 μs. The average power consumption for a single-channel stimulation is 38 mW from a 1.2 V power supply. This implantable stimulator system was simulated in HSPICE using 90 nm CMOS technology.

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

Concurrent Calculations on Reconfigurable Logic Devices Applied to the Analysis of Video Images

This paper presents the design and implementation on FPGA devices of an algorithm for computing similarities between neighboring frames in a video sequence using luminance information. By taking advantage of the well-known flexibility of Reconfigurable Logic Devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexing. The experimental results show the tradeoff between concurrent sequential resources and the functional blocks needed to achieve maximum operational speed while achieving minimum silicon area usage. To evaluate system efficiency, we compare the performance of the hardware solution to that of calculations done via software using general-purpose processors with and without an SIMD instruction set.

Fully Symmetrical Monolithic Transformer (True 1 : 1) for Silicon RFIC

A novel on-chip transformer configuration that gives an identical inductor pair, a higher individual coil self-resonant frequency (SRF), and excellent area efficiency are presented. This technique involves the unique way of inter-crossing the transformer's primary and secondary coils using multiple metallization layers. Truly symmetrical transformer configuration (100%) is demonstrated using minimum die size. Thus, a true 1 : 1 transformer has been realized on silicon. The effects of the parasitic within the transformer are represented by an equivalent-circuit model. Accurate semiempirical expressions describing the circuit components are provided based on the various layout parameters. Of all the transformer structures presented, the two designs occupying the minimum silicon area by a factor of > 2× have been selected for performance evaluation of the SRF, coupling coefficient, input impedance, quality factor, and inductance. The transmission line transformer mode has also been studied to examine the designs' performance in the differential mode. The second proposed design reported in this paper, with enhancements in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> 21 and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> performance, is created by adding a unique routing technique onto the first proposed structure. The method presented is fully compatible with the standard foundry CMOS processes. The silicon data reported in this study are based on chartered semiconductor manufacturing's 0.13-mum RF CMOS technology node.

An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors

We present a neural stimulator chip with an output stage (electrode driving circuit) that is fail-safe under single-fault conditions without the need for off-chip blocking-capacitors. To miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled resistors implemented by MOS transistors in the deep triode region. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection using a high-frequency current-switching (HFCS) technique. Unlike conventional stimulator output stage circuits for implantable functional electrical stimulation (FES) systems which require blocking-capacitors in the microfarad range, our proposed approach allows capacitance reduction to the picofarad range, thus the blocking-capacitors can be integrated on-chip. The prototype four-channel neural stimulator chip was fabricated in XFAB's 1-mum silicon-on-insulator CMOS technology and can operate from a power supply between 5-18 V. The stimulus current is generated by active charging and passive discharging. We obtained recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with the stimulator chip which demonstrate the HFCS technique. The average power consumption for a typical 1-mA 20-Hz single-channel stimulation using a book electrode, is 200 muW from a 6 V power supply. The silicon area occupation is 0.38 mm(2) per channel.

Noise-Insensitive Digital BIST for any PLL or DLL

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure 1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.

Area-Efficient Min-Sum Decoder Design for High-Rate Quasi-Cyclic Low-Density Parity-Check Codes in Magnetic Recording

We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited; 2) the decoder circuit critical path may be greatly reduced; and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.

70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS

This paper examines a time-base measurement system for on-chip digitization. Undersampling, combined with single-path time-domain amplification and processing, is used to perform the embedded measurement in a time-efficient manner. The proposed system relies on simple circuit components while performing high-speed measurements. Additionally, ease of calibration with minimal silicon area overhead renders the system attractive from a design-for-test perspective. The circuit was implemented in a 0.18-mum standard digital CMOS process using a single 1.8-V supply. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using the prototype chip. An effective 70-GHz sampling rate is experimentally obtained from the implemented on-chip oscilloscope, with a voltage resolution of 4 mV. The estimated static power dissipation is ~3.5 mW, with a total active area of 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> taken up by the associated test and calibration vehicles.