Minimization Of Switching Functions Research Articles

Novel Quantum Algorithms to Minimize Switching Functions Based on Graph Partitions

After Google reported its realization of quantum supremacy, Solving the classical problems with quantum computing is becoming a valuable research topic. Switching function minimization is an important problem in Electronic Design Automation (EDA) and logic synthesis, most of the solutions are based on heuristic algorithms with a classical computer, it is a good practice to solve this problem with a quantum processer. In this paper, we introduce a new hybrid classic quantum algorithm using Grover’s algorithm and symmetric functions to minimize small Disjoint Sum of Product (DSOP) and Sum of Product (SOP) for Boolean switching functions. Our method is based on graph partitions for arbitrary graphs to regular graphs, which can be solved by a Grover-based quantum searching algorithm we proposed. The Oracle for this quantum algorithm is built from Boolean symmetric functions and implemented with Lattice diagrams. It is shown analytically and verified by simulations on a quantum simulator that our methods can find all solutions to these problems.

Minimization of Switching Functions using Quine-McCluskey Method

The minimization of switching functions is important to reduce the original number of logic gates required to implement digital logic circuits. Quine-McCluskey algorithm is classical method for simplifying these functions which can handle any number of variables. This paper presents Quine-McCluskey algorithm for minimizing switching functions, with additional specific elements, such as starting part (that is decoding DNF form) and cost of circuit. An example of implementation of the algorithm is given too.

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

The synthesis of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits, and a number of efficient algorithms have been proposed. The paper reports new techniques that facilitate designing such space-efficient BIST support circuits using knowledge of compact test sets, with the target objective of minimizing the storage requirements for the circuit under test (CUT), while retaining the fault coverage information. The suggested techniques take advantage of some well-known concepts of conventional switching theory, particularly those of cover table and frequency ordering, as commonly utilized in the minimization of switching functions, in conjunction with a new measure of failure probability in case of stochastic dependence of line errors, besides knowledge of Hamming distance, sequence weights, and derived sequences as previously used by the authors in sequence characterization, in the selection of specific logic gates for merger of an arbitrary number of output bit streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor to derive the CUT signatures. The techniques give good design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are provided, and the simplicity and ease of their implementations are demonstrated. In particular, the paper gives results on extensive simulation runs on the ISCAS 85 combinational benchmark circuits with ATALANTA, FSIM, and COMPACTEST programs.

Derivation of the Complete Sum of a Switching Function with the Aid of the Variable-entered Karnaugh Map

The complete sum (CS) of a switching function f is defined as a sum-of-products formula whose products constitute all, and nothing but, the prime implicants of f It has many useful applications including the simplification and minimization of switching functions, proving equivalence or independence, solution of Boolean equations, and transient hazard analysis. This paper presents two novel techniques for deriving the CS with the aid of the variable-entered Karnaugh map (VEKM); a map that enjoys several pictorial advantages and a doubled variable-handling capability, and hence is recommended when the number of variables ranges from 7 to 12 or even more. Only completely specified switching functions (CSSFs) are considered herein, simply because the CS of an incompletely specified function f is that of the CSSF that represents the upper bound for f. Our first technique uses the VEKM for obtaining any product-of-sums expression for the function which can be multiplied out to produce the CS after deletion of any absorbable terms. The second technique starts with a VEKM of CS entries, and after repeated folding of the VEKM ends up with the required CS provided necessary absorptions are implemented after each folding. Both techniques gain much from the use of a novel multiplication matrix that restricts the number of term comparisons needed for implementing absorptions. This matrix can be used to advantage also with some purely algebraic techniques such as Tison method. However, algebraic techniques, even after improvement, might remain inferior to VEKM techniques, obviously since the latter can combine most merits of map and algebra. Dual versions of the VEKM techniques considered can be used to obtain the dual of the complete sum, viz., the complete product.

Further Improved Variable-Entered Karnaugh Map Procedures for Obtaining the Irredundant Forms of an Incompletely-Specified Switching Function

Out of the potpourri of methods available for traditional minimization of switching functions, the method of the Karnaugh map is distinguished as a quick manual method that provides the user with pictorial insight. An advanced version of this map, viz., the variable- entered Karnaugh map (VEKM) doubles the variable-handling capa- bility of the map and allows its use for big Boolean algebras. The present paper offers a novel exposition of the essential features and properties of the VEKM, many of which are published for the first time. It also presents a simple and further improved VEKM procedure that obtains one of the irredundant disjunctive forms (IDFs) of an in- completely specified switching function (ISSF). Duality concepts are used to convert the present procedure into a dual one that obtains an irredundant conjunctive form for an ISSF. These procedures differ from their predecessors in two respects. First, the present procedures are rather advanced ones equipped with an explicitly stated set of rules that are clearer, though more powerful, than those of the preced- ing procedures. Second, the present procedures are more precise in handling the contributions of a map entered term, or alterm, and hence are more likely to capture minor details in the intrinsic structure of the ISSF under consideration. Therefore, the present procedures, if fol- lowed strictly, are more likely to achieve exact minimality, and even if not, the resulting expressions from them are always guaranteed to be almost minimal. Many detailed examples are given to demonstrate the essential features and properties of the map and to illustrate the rules and steps of the new procedures.

CAD for Pneumatic Circuit Design in Low Cost Automation

This paper describes the design of a CAD system for pneumatic sequential control. A special language for describing the sequence is developed. The procedure of memory designation and function generation, switching function minimization, and circuit construction is described in detail. Referring to a simple design problem, the computer process from the high level language statement to the pneumatic circuitry is illustrated. Finally, the application of the design package to other control problems is outlined.

A Local Selection Algorithm for Switching Function Minimization

The minimization algorithms which do not require any preliminary generation of all the prime implicants (PI's) of a function are the most efficient. In this work a new algorithm is described which follows such an approach. It is based on a local selection of PI's carried out by examining a set of vertices whose number is never greater than the number of PI's of a minimum cost cover. This algorithm takes advantage of a technique which uses numerical equivalents of the function vertices as pointers. For this reason it is well suited for implementation by computer. To illustrate the features of this algorithm a few examples are reported.

A Graph Theoretic Approach to Switching Function Minimization

In this paper we pursue the graph theoretic approach to the switching function minimization problem which is still important in view of today's technological innovations such as programmable logic arrays. We use switching functions graphs (SFG) for studying the structure of switching functions and the minimization problem. The graph theoretic interpretation of the classical minimization problem leads to an alternative and powerful approach to logic design that is suitable for computer implementations. The approach is particularly useful in the analysis and design of suboptimum algorithms for minimization of arbitrarily complex switching functions arising in practice for which exact algorithms are known to be computationally intractable. A few graph theoretic algorithms leading to minimization of switching functions are presented and examples indicating the power of our approach, and algorithms are worked out. Further work needed in the area is indicated.

A simpler method for minimization of switching functions

A method for finding out the prime implicants and hence the minimal sum(s) of switching functions containing essential prime implicants, cyclic type prime implicants or functions with don't care terms has been suggested in this paper. This paper describes a simpler procedure for sorting out the EPIs while forming the combination tables and to select the other essential terms needed for the minimal cover of the function by a new technique known as the “Formation of combination chain” decribed in the method. The method thus does away with the need for the successive PI tables as suggested in Q-M method.

Minimization of switching functions—an integrated approach

In this paper an integrated method for minimization of switching functions is presented in which the generation and selection of prime implicants (PI) are interleaved. A method for generation of PI's incident on a given minterm has been described and a basis for selection or a PI as an element of the cover from a small subset of PI's has been established. The method presented for minimization of a completely specified switching function has also been extended for an incompletely specified switching function.

A New Technique for the Fast Minimization of Switching Functions

The minimization of switching functions involving many variables is a difficult task. This paper presents a new minimization procedure that allows this process to be implemented with reduced computational effort. This procedure, designated as the directed-search algorithm, is applicable to both manual and computer-programmed minimization. The details of the algorithm are presented and illustrated by example. Comparative run-times between another minimization program and the directed-search algorithm, as implemented in Fortran, are also given.