MIM Capacitance Research Articles

Atomic Layer Deposition of HfAlOx for High-k Gate Dielectrics

Nowadays, the downscaling of CMOS devices requires continued effort to propose high performance components with extremely compact size. Surely, this trend is not achievable without extremely enhanced High-k gate stack materials, inter alia. For years, HfO2-based dielectrics deposited using ALD (Atomic Layer Deposition) technique are perfect dielectrics of choice for various devices and applications (Memristor, resistive random access memory, ferroelectric random access memory, antiferrolectric capacitances, ferroelectric FET...).As such, HfAlOx films present a good compromise between HfO2 and Al2O3 in term of coupling properties and insulating capabilities in comparison with both single HfO2 and Al2O3 films. The purpose of this work is to evaluate binary high-k HfAlOx dielectrics deposited by ALD technique. ALD is well suited for deposition of ultrathin films with exceptional capabilities enabling precise thickness, stoichiometry control and conformal growth at atomic scale. In this work, we focused on Al2O3/HfO2 films fabricated using two approaches: (i) repeatedly alternating the deposition of two different and separate extremely thin oxides (Al2O3 and HfO2; particular focus on HfO2/Al2O3/HfO2/Al2O3/HfO2 multilayer stack with equivalent Al fraction around 30%); (ii) combination of ALD super cycles allowing the formation HfAlOx layers. We analyze the general performance and the behavior of the binary high-k HfAlOx dielectrics (10 nm thin layers deposited at 300°C using TiCl4-TMA-H2O precursors) using physico-chemical (X-ray photoelectron spectroscopy XPS, X-ray reflectometry XRR, wavelength dispersive X-ray fluorescence WDXRF) and electrical measurements (Hg probe measurements, MIM capacitance).The incorporation of Al2O3 in the composition of the HfO2 gate dielectrics allows a perfect monitoring of physico-chemical properties varying from HfO2 layers to Al2O3 layers by controlling the number of Al2O3 and HfO2 ALD cycles. In this respect, we were able to monitor the Al fraction in the range of 5% to ~86% in the mixed binary dielectrics (Figure 1: XRR density of mixed binary layers vs Al/[Al+Hf] ratio, Figure 2: Al and Hf fractions in the mixed layer determined by WDXRF and XPS analysis).The electrical characteristics of the HfAlOx dielectrics confirm the influence of the Al fraction in the HfO2 layer. The leakage currents of the mixed layers decreases with increasing the Al fraction (Figure 3: J/E characteristics of mixed and stacked HfAlOx layers). The breakdown voltages for all mixed HfAlOx layers are greater than that of reference HfO2 layer. On the other hand, the shown multilayer presents an intermediate leakage currents profiles between the two mixed HfAlOx (25%Al and 40%Al). Thus, the incorporation of Al in the construction of HfAlOx system is likely to decrease the number of defects. Furthermore, the fully integrated MIM structures exhibit areal capacitance in the range 10-15 nF/mm2 of ALD-based high-k HfAlOx (10 to 12 nm) depending on the Al fraction. Thus, ALD-HfAlOx with various composition highlight the potential tremendous for high-κ capacitances stack for CMOS semiconductor devices. Figure 1

Measurement results of DIPIX pixel sensor developed in SOI technology

The development of integration type pixel detectors presents interest for physics communities because it brings optimization of design, simplicity of production—which means smaller cost, and reduction of detector material budget. During the last decade a lot of research and development activities took place in the field of CMOS Silicon-On-Insulator (SOI) technology resulting in improvement in wafer size, wafer resistivity and MIM capacitance. Several ideas have been tested successfully and are gradually entering into the application phase. Some of the novel concepts exploring SOI technology are pursued at KEK; several prototypes of dual mode integration type pixel (DIPIX) have been recently produced and described. This report presents initial test results of some of the prototypes including tests obtained with the infrared laser beams and Americium (Am-241) source. The Equivalent Noise Charge (ENC) of 86 e − has been measured. The measured performance demonstrates that SOI technology is a feasible choice for future applications.

MIM capacitance variation under electrical stress

Due to strong requirement in term of capacitance voltage linearity, MIM capacitance stability during the whole operating lifetime of the product appears to be a key issue to warrant the reliability of this device. Using a constant current stress, two effects can be noticed on the evolution of the stressed C– V characteristics: a voltage shift to negative bias and a significant increase of the capacitance. Both phenomena have been demonstrated to be strongly correlated and to have the same origin: the trapped charges in oxide, which can generate new dipoles in the dielectric and, as a result, modulate the dielectric permittivity.