Mil Square Research Articles

Lead Forming and Outer Lead Bond Pattern Design for Tape-Bonded Hybrids

Tape automated bonding (TAB) has progressed to such an extent that hybrid devices are now being designed and built with this technology. In contrast with monolithic device configurations, where inner and outer lead bonds are coplanar, the hybrid device requires the leads to descend from the chip top surface level to the substrate level. It is desirable that the leads follow a carefully designed trajectory to match a substrate bonding pattern of a definite repeatable design. Funded by contracts from the U.S. Army Electronics Command (ECOM) and by internal sources, Honeywell Avionics Division developed a number of different designs for lead forming and outer lead bonding. These designs are now matured to the point that they are being standardized and incorporated into manual and automatic bonding equipment built by the Jade Corporation. They are also being submitted to American Society for Testing and Materials (ASTM) for consideration. Early experimentation with lead forming revealed a two-piece forming tool unable to shape the leads to the designed trajectory. This trajectory, where the leads simultaneously descend and spread out, was termed "fan-out on the slope." The lead frame was redesigned to present identical cross-sectional areas for all leads in the bending areas. Persisting alignment problems after forming resulted in the design and trial of a more complex "triple-action" forming tool. Finally because of continued questionable results, the fan-out on the slope approach was abandoned, and a "fan-out on the level" approach was selected, where the lead fan-out is accomplished on the chip top level before the lead descends to the substrate surface. Next, the development effort was directed to standardize tooling for manual and automatic bonding of multiple chip sizes. Resulting were a set of three outer lead bonding patterns: small, medium, and large, corresponding to carder tape window sizes of 5, 7, and 10 mm, respectively. The basic premise was to make use of all the available beam length by excising as close as possible to the Kapton window in order to allow maximum chip sizes in each of the patterns. The small size measures 170 rail square and can accept chips up to 80 mil square and up to 24 leads. The medium-size measures 250 mil square and can accept chips up to 160 mil in largest dimension and up to 40 leads. The large size measures 350 mil and can accept 250-mil chips and up to 48 leads. The small pattern is designed so that, with 10-mil spacing between adjacent pads and 50-mil spacing from the edges, exactly five patterns fit on a 1inch substrate length. With the same 10-mil spacing, exactly two small patterns fit in the space of one large pattern. The lead trajectory of all three patterns is identical up to a point 40 rail from the excise line, inside of which it is matched to the chip layout. A provision is made for vias and corresponding clearance underneath the lead trajectory inside the outer lead bonds

High E-field microwave properties of bulk amorphous semiconductors

The effects of high microwave electric fields on bulk amorphous semiconductors were studied at room temperature. Samples of eight different glasses were mounted in the center of a reduced height, X-band waveguide in a sandwich geometry parallel to the electric field of the dominant mode. Samples were 90 mil (2.286 mm) square by 8.5 mil (0.2159 mm) thick with thin-film CrAu electrodes. The microwave conductivity remained constant at field strengths below a critical value near 10 4V/cm. Above this value, which depends upon the microwave pulse length, switching to a low-resistance state was observed with the thermal breakdown as the switching initiation mechanism.

Clocked CMOS calculator circuitry

A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail. The CMOS-LSI includes 3300 elements and has a chip size of about 200 mil square, operates at 6 V supply voltage, and dissipates power of about 1 mW at a clock frequency of 50 kHz.

N-p JUNCTION PHOTOVOLTAIC DETECTORS IN PbTe PRODUCED BY PROTON BOMBARDMENT

n-p junction photovoltaic detectors in PbTe have been fabricated using proton bombardment to create the n-type layer. At 77°K, zero-bias resistance area products of 300 Ω cm2 were observed for diodes with dimensions as large as 15 mil square. Peak detectivities at 5 μm in reduced background as high as 3.3×1011 cm Hz1/2/W were observed. Diode quantum efficiencies were typically greater than 30% at 5 μm.

Character Legibility and Digital Facsimile Resolution

Character legibility was measured as a function of facsimile device parameters (pitch and sampling distance, and scan orientation) and of source document parameters (character height and case). The results indicate (I) very slight average difference in legibility (less than 1%) due to scan direction; (2) a more substantial difference (about 9%) between upper and lower case; and (3) legibility directly proportional to pitch and sampling distances, and to character height. For individual characters in standard typescript or similar material, 97.5% legibility apparently requires resolution on the order of 110 × 110 elements to the inch (scanning aperture nine mils square). Two secondary comparisons established the fact that individual character legibility (a) remained virtually unchanged when continuous scanning (one-mil resolution) was substituted for the best (five-mil) sampling distance, and (b) varied less than 2% when extra test documents were generated to check the repeatability of the experiment.

Evaluation of Passivated Integrated Circuits Using the Scanning Electron Microscope

By examining passivated silicon integrated circuits in the scanning electron microscope, the surface contours of p‐n junctions have been mapped, potential drops across integrated resistors have been observed, and physical characteristics of the oxide surface, evaporated leads, and bonded gold wires have been determined. Typical faults discovered by this method of testing include poor registration, improperly masked diffusions, harmful and nonharmful surface scratches, poor evaporated interconnections, and defective passivation oxide layers. Most junctions in a 40 mil square integrated circuit can be delineated with 1μ resolution in approximately 1 min by this technique.

Cost-size optima of monolithic integrated circuits

A generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. It is intended to reveal cost trends rather than give accurate results for specific cases and deals only with fabrication costs. A yield-area relationship is used which takes into account chip-to-chip variations in defect density. It is found that the ratio (circuit cost per component/cost of discrete transistor) is a minimum at a chip size which is determined primarily by the spot defect density on the device. This optimum chip size lies between approximately 20 and approximately 60 mils square for a wide range of parameter values. State-of-the-art parameter values indicate a potential order of magnitude cost saving in integrated circuits compared with discrete transistors. The minimum value for the cost ratio is in general inversely proportional to the maximum packing density of components on a semiconductor slice and has a limiting value approximately 1/8N, N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf> being the number of components which can be packed on the chip size normally used for transistors. Arrays of identical logic gates fit the circuit model used quite closely, and the curves indicate that the cost per gate in reasonably densely packed arrays can be less than the cost of a discrete transistor. The results also indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.

How to Determine a ‘Comparable Cost’ for Paints

Abstract A formula is given which can be used to calculate the percent solids by volume in paints when the percent solids by weight, weight of paint, and density of volatile component are known. The value obtained then can be inserted into a second formula to determine the comparable cost for paints in dollars per mil square foot. A nomograph is included which can be used to determine both the percent solids by volume and the comparable cost for paints. A sample problem is worked out on the nomograph. 5.4.5