Microwave Power FETs Research Articles

Modeling and characterization of RF and microwave power FETs [book review

This book provides a coherent review of the advanced state of power FET modeling and characterization. It covers the topics of device construction, model selection, device measurement, and model validation in sufficient detail to be truly useful. Although not designed as a university text, the book contains enough math and fundamental to serve as a foundation for a course. This is a well-written and useful text.

Material and Device Characteristics of MBE Microwave Power FETs with Buffer Layers Grown at Low Temperature (300°C)

ABSTRACTMBE GaAs grown at low temperature (300°C) is evaluated for its suitability as a buffer layer for microwave power FETs. Hall effect and capacitance-voltage (C-V) measurements show that low temperature (LT) buffers may have strong deleterious effects on the electronic quality of FET active layers unless they are heat-treated in-situ at 600'C and topped with a thin (∼0. lμm) 600°C GaAs buffer prior to growth of the FET active layer. The voltage isolation properties of the LT buffers are found to be thermally stable to rapid thermal anneals up to 870°C for 10 seconds.Transmission electron microscopy (TEM) cross-sections were examined on FET layers with LT buffer layers which ranged in thickness from 0.1μm to 1.0μm. The TEM reveals a high density (∼1017 cm−3) of small (<100Å) arsenic precipitates in all of the buffer layers studied. In cases where the LT buffer is not heat treated and topped with a thin 600°C GaAs buffer layer, dislocations and arsenic precipitates extend from the buffer layer into the FET active layer. Their presence in the active layer correlates with the degradation in electronic properties observed with Hall effect and CV. Microwave power FETs were measured at DC and 5 GHz. DC and RF results for devices with LT buffer layers are comparable to devices with conventional buffer layers.

A new refractory self-aligned gate technology for GaAs microwave power FETs and MMICs

The authors fabricated GaAs power FETs and microwave ICs using a novel fully planar, refractory self-aligned gate process. This process uses methods to reduce the gate resistance and output conductance without sacrificing simplicity. Because it is compatible with the use of an optical stepper, the process is suitable for manufacturing use. The C-band RF performance is excellent; the very uniform and reproducible device parameters resulted in a first-iteration 2.5-W C-band power amplifier that met design specifications on the first lot of wafers processed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of an FET amplifier using power-dependent S-parameters

The paper describes a method to derive large-signal S-parameters as functions of the output power with application to calculating the large-signal power gain of an FET amplifier. The S-parameter S22 of a microwave power FET is used to describe the nonlinearity of its large-signal output impedance, based on which the output at a given load is determined from the measured data. The large-signal S-parameters of the FET can be expressed as a quadratic function of the output power, and are used to compute the gain compression effect of the FET amplifier. This is found to be in good agreement with experimental results.

Buried-shallow-implant (Bsi) process for High Efficiency Microwave power Mesfets

ABSTRACTWe present a hybrid implant epitaxy process that alleviates the inherent depth-width-dependent limitation of ion implantation. This technique allows shallow implants, which produce a thin active N layer with a controlled doping gradient, to be buried at an arbitrary depth below the less-critical, epitaxiallygrown surface layer. The formation and characteristics of GaAs buried shallow-implant (BSI) layers for microwave power FETs will be discussed.

Investigation of In0.53Ga0.47As for high-frequency microwave power FET's

Submicrometer In 0.53 Ga 0.47 As junction field-effect transistors (JFET's) were fabricated using a chemical etching technique. In spite of the well-known low bulk breakdown fields of InGaAs, the source-drain breakdown voltages of the FET's were close to 20 V under pinchoff conditions, indicating a potentially high power-handling capability. At 11 GHz, a 250-µm-wide FET showed a linear gain of 5.2 dB and 17.2-dB . m (53 mW) output power at 1-dB compression point, with a power-added efficiency of 14 percent. Problems of an unexpectedly low electron mobility in the channel, annealing of implanted Be, and oscillations in the drain current-voltage characteristic are discussed.

RF Characterization of Microwave Power Fet's

The large-signal S-parameter S/sub 22/ and the optimum load for maximum output power are two parameters commonly used in the RF characterization of microwave power FET's. Using a nonlinear circuit model of the device, the dependence on RF power of each of these parameters is investigated. A method is given for computing the optimum load from the Iarge-signal S/sub 22/. Equivalent load-pull data can thus be obtained without the need for load-pull measurements. The gain compression characteristics of the transistor for arbitrary load can be computed from large-signal S/sub 21/, and S/sub 22/ data.

GaAs microwave power FET with polyimide overlay interconnection

An overlay interconnection technology has been developed for GaAs microwave power FETs, using polyimide as an insulator. An output power of 1017 mW at 4.3 dB gain was achieved at 8 GHz with 27° power added efficiency from a device with a gate width of 1.2 mm. Comparison with devices without overlay interconnection and having a narrower gate width revealed no evidence for degradation in device performance attributable to the interconnection technology.

GaAs microwave power FET

A design consideration for an X-band GaAs power FET, features of the fabrication process, and electrical characteristics of the FET are described. Interdigitated 53 source and 52 drain electrodes and an overlaid gate electrode for connecting 104 Schottky gates in parallel have been introduced to achieve a 1.5-µm-long and 5200-µm-wide gate FET. A sheet grounding technique has been developed in order to minimize the common source lead inductance (L 8 = 50 pH). The resulting devices can produce 0.7-W and 1.6-W saturation output power at 10 GHz and 8 GHz, respectively. At 6 GHz, a linear gain of 7 dB, an output power of 0.85 W at 1-dB gain compression and 30-percent power added efficiency can be achieved. The intercept point for third-order intermodulation products is 37.5 dBm at 6.2 GHz.