Microelectronic Fabrication Research Articles

Single-Walled Carbon Nanotube Based Field-Effect Transistors Functionalized with Odorant Receptors for Biosensing Applications

Bioelectronic detection of volatile organic compounds (VOC) has been demonstrated in a wide range of applications, with early reports focusing on environmental exogenous VOCs due to their adverse effects on human health; bacterial VOC signatures used as disease biomarkers, etc. Carbon nanotube field-effect transistors (CNT-FETs) are considered promising devices for bioelectronic detection due to their sensitivity, robustness and compatibility with microelectronic fabrication technologies. However, implementation of CNT-FETs still faces many challenges. Current VOCs detection approaches rely on separation techniques coupled with mass spectrometry, necessitating expensive equipment, labor-intensive preparation steps and trained personnel, and are not suitable for field use. Overcoming the challenges in the development of bioelectronic CNT-FET sensors holds great promise for high-throughput screening of VOCs.The natural insect odorant receptors (ORs) are highly attractive probes, potentially allowing ultrahigh specificity for VOC biosensing. Insect ORs exhibit remarkable sensitivities and the ability to selectively detect a vast number of VOCs. We have recently developed OR-functionalized carbon nanotube field-effect transistor (FET) devices. These FET devices comprise an isolated single-walled carbon nanotube (SWCNT), serving as the conducting channel material, functionalized with multiple insect ORs. These hybrid devices are capable of transducing ligand binding into an electronic current, without amplification. The insect OR-functionalized CNT FET were applied for the detection of several markers of environmental and clinical importance including Indole, Skatole, Octen-3-ol and Nonyl-aldehyde.We have developed a bioelectronic assay platform that contains a chip with 61 ORs-functionalized CNT-FET devices. Our unique functionalization method is based on directing the attachment of a native ORs-containing nanovesicles (which we have exogenously expressed and functionally characterized) to a generated CNT-FET point defect. Target binding-induced ionic current and conformational changes of ORs affect an electric field that modulates the device conductance.

DMD digital lithography optimization based on a hybrid genetic algorithm and improved exposure model

An efficient method to optimize digital micromirror device (DMD) lithography was proposed using a hybrid genetic algorithm integrated with an improved exposure model. The improved exposure model significantly refines traditional approaches by incorporating advanced parameters not previously considered, including the cross-transfer coefficient, detailed light source functions, and impulse response functions. These enhancements provide a comprehensive assessment of the entire optical imaging system’s impact on lithography quality and more accurately simulate the interactions of light with the photoresist. The hybrid method combines the robust optimization capabilities of genetic algorithms (GA) with this sophisticated exposure model, facilitating precise micromirror configurations and optimizing light distribution for specific lithographic patterns. This integration results in substantial improvements in lithographic precision, with improvements of up to 84% for hexagonal star patterns, 83% for arrow patterns, and 85% for embedded figure patterns. These advancements enhance imaging quality, reduce optical proximity distortions, and improve overall lithography performance, offering crucial insights into the precision and efficiency improvement of microelectronics fabrication processes.

Inverse-designed metasurfaces with facile fabrication parameters

Optical metasurfaces are planar nanostructured devices that are industrially attractive in part because they utilize high-throughput microelectronic fabrication techniques for implementation. It is therefore critical to develop design paradigms that can balance the realization of highly efficient wavefront responses together with device manufacturability. We introduce a gradient-based design framework for freeform metasurfaces in which nanoscale elements are explicitly constrained to feature basic shapes, nearly uniform feature sizes, and exceptionally low aspect ratios. In spite of the apparent uniformity of the metasurface geometric features, the devices are able to utilize nonlocal near-field optical coupling to achieve highly efficient and extreme wavefront scattering beyond conventional design methodologies. Utilizing this approach, we design facile high-numerical-aperture devices such as beam deflectors and large-area metalenses capable of diffraction-limited focusing. We anticipate that these concepts can facilitate the design and integration of metasurfaces into monolithic optical systems.

Voltage waveform tailoring for high aspect ratio plasma etching of SiO2 using Ar/CF4/O2 mixtures: Consequences of low fundamental frequency biases

The use of non-sinusoidal waveforms in low pressure capacitively coupled plasmas intended for microelectronics fabrication has the goal of customizing ion and electron energy and angular distributions to the wafer. One such non-sinusoidal waveform uses the sum of consecutive harmonics of a fundamental sinusoidal frequency, f0, having a variable phase offset between the fundamental and even harmonics. In this paper, we discuss results from a computational investigation of the relation between ion energy and DC self-bias when varying the fundamental frequency f0 for capacitively coupled plasmas sustained in Ar/CF4/O2 and how those trends translate to a high aspect ratio etching of trenches in SiO2. The fundamental frequency, f0, was varied from 1 to 10 MHz and the relative phase from 0° to 180°. Two distinct regimes were identified. Average ion energy onto the wafer is strongly correlated with the DC self-bias at high f0, with there being a maximum at φ = 0° and minimum at φ = 180°. In the low frequency regime, this correlation is weak. Average ion energy onto the wafer is instead dominated by dynamic transients in the applied voltage waveforms, with a maximum at φ = 180° and minimum at φ = 0°. The trends in ion energy translate to etch properties. In both, the high and low frequency regimes, higher ion energies translate to higher etch rates and generally preferable final features, though behaving differently with phase angle.

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

Broadband Microelectromechanical Systems‐Based Silicon Nitride Photonic Switch

Over the past three decades, silicon photonic devices have been core to the realization of large‐scale photonic‐integrated circuits. However, silicon nitride is another key complementary metal oxide semiconductor‐compatible material for high‐density photonic‐integrated circuits, having low manufacturing costs, low optical losses, and excellent mechanical properties, that can provide enhanced performance over silicon in an integrated photonic platform. This article presents the design, fabrication, and testing of a proof‐of‐concept switchable silicon nitride photonic coupler that leverages these properties combined with microelectromechanical systems actuation. The photonic platform uses a moveable suspended waveguide to enable efficient out‐of‐plane switching and is built using conventional lithographic techniques to demonstrate the high compatibility with existing microelectronic fabrication techniques. The photonic switch is measured to have an insertion loss of 2.6 dB and an ON/OFF extinction ratio of 34 dB at the output of the suspended waveguide, at a wavelength of 1470 nm. Detailed simulations demonstrate broadband operation over a 600 nm wavelength range from 1.25 to 1.85 μm which is experimentally validated over the range from 1.25 to 1.61 μm. To the best of knowledge, this is the broadest operation range ever demonstrated by a photonic switch in simulation.

Flexible Carbon Nanotube-Epitaxially Grown Nanocrystals for Micro-Thermoelectric Modules.

Flexible thermoelectric materials have attracted increasing interest because of their potential use in thermal energy harvesting and high-spatial-resolution thermal management. However, a high-performance flexible micro-thermoelectric device (TED) compatible with the microelectronics fabrication process has not yet been developed. Here a universal epitaxial growth strategy is reported guided by 1D van der Waals-coupling, to fabricate freestanding and flexible hybrids comprised of single-wall carbon nanotubes and ordered (Bi,Sb)2 Te3 nanocrystals. High power factors ranging from ≈1680 to ≈1020 µW m-1 K-2 in the temperature range of 300-480 K, combined with a low thermal conductivity yield a high average figure of merit of ≈0.81. The fabricated flexible micro-TED module consisting of two p-n couples of freestanding thermoelectric hybrids has an unprecedented open circuit voltage of ≈22.7 mV and a power density of ≈0.36 W cm-2 under ≈30 K temperature difference, and a net cooling temperature of ≈22.4 K and a heat absorption density of ≈92.5 W cm-2 .

A Review on Silicon Nanowires and their use in the Development of Nano Piezoresistive Pressure Sensors

Abstract: Silicon has been the most trusted and used material in the fabrication of microelectronics components and systems. Recently, silicon nanowires have gained a lot of importance in the development of devices/components in many applications. SiNWs have unique attributes that are not found in bulk silicon. Their one-dimensional electronic structure provides interesting properties. Unique properties and small dimension (nm) of silicon nanowires have made them to be used as sensing elements in the development of nanosensors and devices. Silicon nanowires are now being extensively used in the development of biosensors, FETs, lithium-ion batteries, transistors, microelectronic chips, and sensors. SiNWs are used in the development of solar cells and photovoltaic batteries, because of their charge-trapping capabilities. The fabrication of silicon nanowires follows chemical etching, chemical vapor deposition (CVD), electron beam lithography, etc. The dimensions of silicon nanowires are highly compatible with the dimensions of biological and chemical species, hence making them more efficient to be used as sensing elements in bio and chemical domains. SiNWs exhibit excellent piezoresistive properties and hence are used as piezoresistors in piezoresistive sensing applications. This article presents a review of SiNWs in the development of sensors. An emphasis is given to the piezoresistive property of SiNWs. The use of SiNWs as a piezoresistor in the development of piezoresistive pressure sensors is also extensively reviewed in this article, along with the unique properties of SiNWs. Typical dimensions and applications of SiNWs are also reviewed. Moreover, this article also explores the fabrication, characterization aspects, and capabilities of SiNWs in the design and development of nanoscale devices/sensors.

Study on the properties of wafer-scale grown MoS2 deposited via thermally induced chemical vapor deposition with Mo(CO)6 and H2S precursors

To realize profitable applications with 2D-materials the transition from research scale to microelectronic fabrication methods is needed. This means the use of equipment for larger substrates and assessment of the process flows. In this study we demonstrate an effective way to assess MoS2 as semiconducting material, deposited with the lower priced precursors Mo(CO)6 and H2S on 200 mm silicon wafers. We could show how the evolution of layer quality develops depending on temperature and interface pretreatment. It is not possible to achieve mono-layers of 0.6 nm with high quality due to seeding kinetics and mechanism. In contrast, layers with thicknesses above 3 nm have suitable electrical and optical qualities to proceed with the design of active devices on 200 mm wafers.

Kinetic and in Situ Analysis for Ion Transport Process in Copper Electrodeposition Using Polyelectrolyte Membranes

Electrodeposition of metals has been one of the most important techniques for fabrication of microelectronics and semiconductor elements in printed circuit boards and electronics device manufacturing. From the industrial perspective, the management of electrodeposition bath is crucial to maintain product quality, productivity and long-term stability of the bath, the subject of which includes bath temperature, concentration of metal salts, supporting electrolytes, and various additives. Although these parameters have been optimized to achieve desirable deposition rate, depending on the product type and morphology, some environmental issues regarding with generating mist, sludges, and waste effluent during electrodeposition process are becoming apparent. Additionally, current electrodeposition process has been developed for substrates with large surface area and for large scale production of electronic components and could not be suitable for recent demand of small-lot, site-selective and multiproduct device microfabrication. Therefore, high-performance deposition system, allowing site-selective electrodeposition of metals without generation of large amount of effluents, needs to be developed to impact above environmental and cost perspectives. Recently, we reported a novel method for electrodeposition of metals using polyelectrolyte films attached on cathode substrate (solid electrodeposition: SED) [1]. The SED process enables one to deposit metals directly on the cathode surface from metal ions inside solid polyelectrolyte membranes and has desirable advantages including higher deposition rate, site-selectivity, and deposition using lower concentration electrolyte solution without additives. In this SED process, thin polyelectrolyte membrane sandwiched between electrodes effectively concentrates metal ions through interfacial penetration, which increases the conductance between the electrodes and realizes solid-state electrodeposition that produces no mist, sludge, or even waste effluent.In this study, we present mechanistic analysis of the SED process, including transport kinetics and equilibrium reaction of copper ions at solution/membrane interface (Figure A). We show that both detailed experimental results and theoretical calculations reveal that ion transfer in the present electrodeposition system is a penetration-controlled process at the solution/polyelectrolyte interface, providing an inherently different ion-transport mechanism compared to that of conventional diffusion-controlled electrodeposition. Several parameters including penetration rate constant, electrode geometry, and distance between polyelectrolyte and anode are varied to investigate the ion-transport process in the SED system. When the anode is slightly apart from polyelectrolyte film to introduce electrolyte layer but is closer as far as possible to it, greater current density for copper electrodeposition is achieved at steady state than that for the systemwhere the membrane is sandwiched by electrodes (Figure B). This can be due to maximum ion penetration rate and minimum resistivity of electrolyte layer, providing better deposition setup for high performance electrodeposition. Additionally, we also performed in situ analysis of concentration of copper ions inside polyelectrolyte film via visible absorption spectroscopy using a miscofiber during electrodeposition. As a result, concentration of copper in the polyelectrolyte film decreased initially and then became constant (steady state) as the deposition proceeded, a fashion of which was quite similar with that of current-time curves simultaneously acquired during constant-voltage electrodeposition.The developed deposition setup demonstrates stable electrodeposition of copper using aqueous copper sulfate solution with no supporting electrolytes and/or additives at deposition rate of few micrometers per minute. As a site-selective deposition tool, the SED process can be used to fabricate microelectronic and even semiconductor circuit elements in a manner that resembles stamping deposition, and is suitable for small-lot, on-demand, and multi-product microfabrication.Reference:[1] K. Akamatsu, S. Nakano, K. Kimura, Y. Takashima, T. Tsuruoka, H. Nawafune, Y. Sato, J. Murai, H. Yanagimoto, ACS Appl. Mater. Interfaces, 13 (2021) 13896-13906. Figure 1

Foundations of plasma enhanced chemical vapor deposition of functional coatings

Since decades, the PECVD (‘plasma enhanced chemical vapor deposition’) processes have emerged as one of the most convenient and versatile approaches to synthesize either organic or inorganic thin films on many types of substrates, including complex shapes. As a consequence, PECVD is today utilized in many fields of application ranging from microelectronic circuit fabrication to optics/photonics, biotechnology, energy, smart textiles, and many others. Nevertheless, owing to the complexity of the process including numerous gas phase and surface reactions, the fabrication of tailor-made materials for a given application is still a major challenge in the field making it obvious that mastery of the technique can only be achieved through the fundamental understanding of the chemical and physical phenomena involved in the film formation. In this context, the aim of this foundation paper is to share with the readers our perception and understanding of the basic principles behind the formation of PECVD layers considering the co-existence of different reaction pathways that can be tailored by controlling the energy dissipated in the gas phase and/or at the growing surface. We demonstrate that the key parameters controlling the functional properties of the PECVD films are similar whether they are inorganic- or organic-like (plasma polymers) in nature, thus supporting a unified description of the PECVD process. Several concrete examples of the gas phase processes and the film behavior illustrate our vision. To complete the document, we also discuss the present and future trends in the development of the PECVD processes and provide examples of important industrial applications using this powerful and versatile technology.

Voltage waveform tailoring for high aspect ratio plasma etching of SiO2 using Ar/CF4/O2 mixtures: Consequences of ion and electron distributions on etch profiles

The quality of high aspect ratio (HAR) features etched into dielectrics for microelectronics fabrication using halogen containing low temperature plasmas strongly depends on the energy and angular distribution of the incident ions (IEAD) onto the wafer, as well as potentially that of the electrons (EEAD). Positive ions, accelerated to high energies by the sheath electric field, have narrow angular spreads and can penetrate deeply into HAR features. Electrons typically arrive at the wafer with nearly thermal energy and isotropic angular distributions and so do not directly penetrate deeply into features. These differences can lead to positive charging of the insides of the features that can slow etching rates and produce geometric defects such as twisting. In this work, we computationally investigated the plasma etching of HAR features into SiO2 using tailored voltage waveforms in a geometrically asymmetric capacitively coupled plasma sustained in an Ar/CF4/O2 mixture at 40 mTorr. The tailored waveform consisted of a sinusoidal wave and its higher harmonics with a fundamental frequency of 1 MHz. We found that some degree of control of the IEADs and EEADs is possible by adjusting the phase of higher harmonics φ through the resulting generation of electrical asymmetry and electric field reversal. However, the IEADs and EEADs cannot easily be separately controlled. The control of IEADs and EEADs is inherently linked. The highest quality feature was obtained with a phase angle φ = 0° as this value generated the largest (most negative) DC self-bias and largest electric field reversal for accelerating electrons into the feature. That said, the consequences of voltage waveform tailoring (VWT) on etched features are dominated by the change in the IEADs. Although VWT does produce EEADs with higher energy and narrower angular spread, the effect of these electrons on the feature compared to thermal electrons is not large. This smaller impact of VWT produced EEADs is attributed to thermal electrons being accelerated into the feature by electric fields produced by the positive in-feature charging.

Diffusivity and solubility of HF gas in polymers and nanocomposites used for automated handling containers of silicon substrates in microelectronic industry

Thermoplastic boxes with internal clean mini-environment (ISO 14644–1:2015, class 2–3), called Front Opening Unified Pods (FOUP), are widely used in microelectronic fabrication for transport and handling of silicon substrates (named wafers) in order to minimize the negative impact of contaminants on integrated circuits. As a type of airborne molecular contaminants (AMC), hydrogen fluoride (HF) outgassed from freshly processed wafers and sorbed (adsorption and absorption) on/in FOUP's walls and then becomes a potential source for subsequent HF cross-contamination. Thin polymeric films which were comprised of available commercial FOUP materials were prepared by hot pressing. They were neat polymers (polycarbonate (PC), Entegris Barrier Materials (EBM)) and nanocomposites (polycarbonate/carbon powder (PCCP), polycarbonate/carbon nanotubes (PCCNT), and EBM/carbon nanotubes (EBMCNT)). The sorption and desorption kinetics of HF in polymers were experimentally established at ultralow HF concentration (part-per-billion-volume, ppbv) and cleanroom conditions (atmospheric pressure, 20 °C and 40%RH); such conditions mimicking fabrication process conditions. Having a polar group in polymeric chains, the PC, PCCP and PCCNT showed a higher affinity to HF rather than EBM and EBMCNT, which resulted in significantly increasing HF diffusivity (nearly two orders of magnitude, 10−10 versus 10−12 cm2.s−1) and HF solubility. The presence of embedded CNT in nanocomposites (PCCNT and EBMCNT) exhibited a significant increase of both HF diffusivity and solubility. Interestingly, based on desorption curves, it was determined that the sorbed HF in nanocomposites made with CNT was composed of two types (i) fixed-HF inside cylindrical voids of CNT and (ii) mobile-HF in polymeric bundle-chains. In addition, the obtained HF transport coefficients were applied as input data in numerical simulation model to simulate the HF concentration profiles and the evolution of HF uptake in FOUP walls in different scenarios.

An Investigation of Tin Electroless Deposition

Electroless metal/alloy deposition can be an efficient process in certain areas of microelectronic fabrication. In fact, it is often easier to obtain coatings of uniform thickness and composition using electroless deposition than with electrodeposition, since one does not have the current density uniformity problem of the latter. For example, we were able to develop a Ni(P) process as a replacement for the final aluminum interconnect level, significantly decreasing wafer processing cycle time, by selectively depositing a Ni(P) capping layer on the Cu bitline wiring level. In STTM MRAM, we successfully employed this Ni(P) capping process to enable the evaluation of memory state retention via functional testing in an air atmosphere at elevated temperatures (1).However, there is a need to explore materials + deposition methods for rapidly developing fields, such as Quantum computing, e.g., materials with superconducting properties. Conventional electroless metal deposition, utilizing a separate reducing agent, can deposit materials with unique and useful properties, such as phosphorus-containing alloys in the case of hypophosphite reducing agents. This talk discusses work we have carried out on electroless tin deposition, including aspects of electroless solution preparation and stability, copper substrate surface preparation and catalyzation, and the mechanisms of electroless deposition and solution decomposition.Electroless processes can deposit a limited number of materials, especially pure metals. This is in part due to conventional electroless processes requiring catalytically active surfaces both to initiate the deposition reaction and to sustain it, the heterogeneous oxidation of the reducing agent being a kinetically hindered process, often with multiple reaction pathways (2). Though not possessing good catalytic activity due to its Periodic Table related, p -block element status, pure Sn, an environmentally robust, superconducting metal, can be electrolessly deposited through a disproportionation reaction involving stannous ions (3) in an alkaline aqueous medium.We achieved electroless Sn deposition rates of up to 8 – 9 μm/hr for tartrate-citrate complexed electroless Sn solutions in the temperature range 80 – 85 ⁰C with sodium and potassium hydroxides to adjust alkalinity. We found that either in-house formulated, or commercially available, immersion Sn solutions deposited a uniform Sn catalyst layer (≤ 0.5 μm) to initiate the electroless Sn deposition reaction on copper; however, improperly formulated immersion Sn solutions rapidly developed precipitates due to tin ion hydrolysis.The biggest technical challenge was minimizing unwanted electroless deposition of tin in bulk solution, i.e., deposition not associated with the catalytically active substrate surface. Tin oxide (SnO) is known to be metastable at ambient conditions and to decompose at temperatures above 300 ⁰C with “noticeable rate” into Sn and SnO2 (4). Thus, removal of filterable hydrolysis products of Sn(II) following solution preparation was important, but not always sufficient, for obtaining solutions that were viable for several days of use. The reasons for, and mechanisms of, electroless Sn solution decomposition do not appear to have been adequately addressed in the literature.We will show SIMS analysis of both immersion and electroless Sn layers along with synchrotron X-Ray analysis results of immersion Sn catalyst films on Cu to determine the extent of Sn-Cu intermetallic formation following their formation. We will discuss the current understanding of the mechanism of electroless Sn deposition including that of concomitant H2 gas evolution. We will conclude with contrasting the Ni(P) and Sn electroless processes in terms of ease of operation and reliability for routine processing. † Present address: Solvay, 1937 West Main Street, Stamford 06902, CT. ‡ Quantum intern at the IBM TJ Watson Research Center, Summer 2019, 2020 and 2021.[1]. E. J. O'Sullivan, C. Camagong et al., 2019 Meet. Abstr. MA2019-02 916; https://doi.org/10.1149/MA2019-02/15/916.[2]. E. J. O'Sullivan, Ch 5, Advances in Electrochemical Science and Engineering, Volume 7, https://doi.org/10.1002/3527600264.ch5.[3]. A. Molenaar and J. W. G. de Bakker, 1989, J. Electrochem. Soc. 136, 378 and refs therein; H. Koyano, M. Kato, and M. Uchida, 1991, Plating and Surface Finishing, 78, 68-74 and refs therein.[4]. H. Giefers et al, 2005, Solid State Ionics, 176, 199-207; https://doi.org/10.1016/j.ssi.2004.06.006. Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out.

Comparison of glancing-angle scatterings on different materials in a high aspect ratio plasma etching process using molecular dynamics simulation

In plasma etching for microelectronics fabrication, one of the objectives is to produce a high aspect ratio (HAR) via and trench structures. A principal contributor to the HAR feature shape is the manner in which energetic ions interact with sidewalls inside the feature. The scattering angle and energy loss of ions reflecting from sidewalls determine the sidewall slope and can lead to defects such as microtrenching and bowing. Understanding how ions interact with sidewalls can improve our control of the critical dimensions of HAR features. Ions accelerated in the plasma sheath arrive in the feature with energies as large as a few keV and initially strike the sidewalls at glancing angles. These scattering events extend to the photolithographic mask. Scattering from the mask at glancing angles can produce ions incident into the underlying feature with a broader angular distribution, leading to less desirable feature properties. In this work, results are discussed from Molecular Dynamics (MD) simulations of glancing-angle scattering of argon ions from three materials common to HAR etch: polystyrene (as a photoresist surrogate), amorphous carbon (a hard mask material), and SiO2 (a common insulating material used in microelectronics devices). Results from simulations reveal a transition from specular scattering to diffuse scattering as the angle of the incident ion decreases (90° being glancing incidence) and incident energy increases. Scattering from polystyrene is more diffuse compared to amorphous carbon and SiO2 for identical incident ion conditions.

The Effect of Molecular Orientation in Disperse Red-1 Film on Its Refractive Index

The refractive index of materials is an important physical quantity in the design of various photonic devices. For thin-film based devices, the fabrication method should be compatible with existing processes in microelectronic fabrication and allow for controlling the refractive index. In this research, the material used is a polar Disperse Red 1 (DR1) molecule. The film fabrication was carried out using the physical vapor deposition method which had been equipped with an electric poling installation. The poling of the electric field during the deposition process was applied perpendicular to the substrate. The thickness measurement and the refractive index of the films were carried out using a reflectometer where the light was incident perpendicular to the substrate. The refractive index was determined by the multiple beam interference method. As a result, it was found that the application of an electric field causes a change in the orientation of the molecules, which were initially parallel to the substrate to become perpendicular. Increasing the field strength further reduces the number of molecules parallel to the substrate. This correlates with a decrease in the refractive index of the film.

Direct Laser Writing of Graphitic Carbon from Liquid Precursors

One-step synthesis and micropatterning of different types of carbon nanomaterials, such as amorphous carbon or three-dimensional graphene which have versatile electrochemical, thermal, and mechanical properties, are advantageous for the fabrication of microelectronics, sensors, and wearable devices. Here, we report a direct laser writing method to simultaneously synthesize and pattern graphitic carbon from liquid organic precursors. We have tested a wide range of liquid organic precursors and identified the chemical characteristics that are beneficial for successful laser-induced solvothermal deposition. The laser-deposited carbon exhibits a paracrystalline-to-polycrystalline structure and has electrical resistivities on the order of 10–3 to 10–4 Ω m which is tunable through variations in the laser power. Such properties of the laser-deposited carbon, coupled with the ability to direct-write custom patterns with microscale resolution, make these carbon materials exciting candidates for use in applications such as energy storage and sensing.

(Invited) Chemical Approaches to Etch and Pattern Copper Films

Microelectronic device fabrication has traditionally been performed by selective removal or etching of material from deposited films to create patterns. Plasma etching has been the mainstay of this process since the early 1970s. The introduction of copper (Cu) metallization (~1997) by IBM resulted in the development of additive approaches (e.g., damascene process) due to the inability to plasma etch Cu. Despite attempts to plasma etch Cu as early as 1980, the only viable plasma-based methods in this time frame were inert gas sputtering, where selectivity to underlying layers and low etch rate were problematic, or chlorinated vapors that required elevated temperatures (>200 C) or significant ion bombardment energies to volatilize Cu chlorides. Both approaches required a hard mask rather than photoresist layers to ensure mask stability and precise pattern transfer. Due to the inability to form high volatility Cu halides that could be removed readily by plasma processes, other non-plasma or partial plasma approaches to Cu etching at lower temperatures were investigated. Addition of a UV lamp to facilitate excitation and desorption of volatile Cu chlorides in plasma etching was invoked. Formation and volatilization of copper by oxidation followed by complexation with organic ligands at lower (~150 C) temperatures was first reported in the mid-1990s, but this processes generated isotropic etch patterns; more recent approaches have reported anisotropy. Plasma chlorination followed by a liquid etch to remove the chlorinated Cu was also reported; due to the directionality of the plasma chlorination step, anisotropic profiles resulted. Hydrogen-based etching of Cu films was reported in 2010, initially with a two-step process consisting of plasma chlorination followed by a hydrogen plasma step to remove volatile products. This effort subsequently demonstrated that etching by pure hydrogen in a one-step process was possible albeit with low etch rates; etch rate increases were observed with vapor additives. Pure hydrogen plasmas etched photoresist layers, thereby requiring hard masks, but additives allowed employment of photoresist as a mask layer. Anisotropic etch profiles from these hydrogen-based processes were possible, in part due to additives protecting sidewalls and photoresist from etching and to ion bombardment during etching.This presentation will describe the development of Cu etching and patterning methods beginning in the 1970s. Mechanistic considerations of the various processes reported will be discussed and the current needs and limitations of these approaches indicated.

Geometric advection and its application in the emulation of high aspect ratio structures

The ability to simulate the processes required to fabricate advanced microelectronic structures, commonly referred to as process technology computer aided design (TCAD), is essential for the semiconductor industry. It aids in the design and development of modern integrated circuits at low cost. Ongoing demands of high efficiency and simplicity lead to the development of process emulation techniques, which describe the effect of a fabrication step by using only the geometric properties gathered from experimental data or extracted from physical simulations. However, the accuracy of current emulation models is limited by their strong reliance on explicit surface representations, while traditional algorithms employing implicit surfaces, such as the level set, can frequently suffer from numerical limitations. A novel geometric advection algorithm for microelectronic process emulation is presented, which advances a level set surface over large distances in a single simulation step. It combines the advantages of explicit surface representations, such as fast access to surface data and efficient sorting, and the robustness of implicit surface representations. Furthermore, calculations are performed directly in the level set avoiding costly conversions to explicit surfaces. The performance and applicability of the algorithm to modern processes is demonstrated by emulating the fabrication of several high aspect ratio structures. Due to the almost universal applicability and computational efficiency of the presented geometric advection algorithm, it provides an entirely new way of emulating microelectronic fabrication processes and presents a promising alternative to long-standing and commonly used techniques.

Multiscale modeling of plasma–surface interaction—General picture and a case study of Si and SiO2 etching by fluorocarbon-based plasmas

The physics and chemistry of plasma–surface interaction is a broad domain relevant to various applications and several natural processes, including plasma etching for microelectronics fabrication, plasma deposition, surface functionalization, nanomaterial synthesis, fusion reactors, and some astrophysical and meteorological phenomena. Due to their complex nature, each of these processes is generally investigated in separate subdomains, which are considered to have their own theoretical, modeling, and experimental challenges. In this review, however, we want to emphasize the overarching nature of plasma–surface interaction physics and chemistry, by focusing on the general strategy for its computational simulation. In the first half of the review, we provide a menu card with standard and less standardized computational methods to be used for the multiscale modeling of the underlying processes. In the second half, we illustrate the benefits and potential of the multiscale modeling strategy with a case study of Si and SiO2 etching by fluorocarbon plasmas and identify the gaps in knowledge still present on this intensely investigated plasma–material combination, both on a qualitative and quantitative level. Remarkably, the dominant etching mechanisms remain the least understood. The resulting new insights are of general relevance, for all plasmas and materials, including their various applications. We therefore hope to motivate computational and experimental scientists and engineers to collaborate more intensely on filling the existing gaps in knowledge. In this way, we expect that research will overcome a bottleneck stage in the development and optimization of multiscale models, and thus the fundamental understanding of plasma–surface interaction.