MHz System Research Articles

Assessment of Radio-Frequency Radiation Exposure from Selected Mobile Base Stations in Yenagoa, Bayelsa State, Nigeria

The antennas from mobile base stations radiate non-ionizing radio frequency radiation into space. The human body can experience negative health effects from prolonged exposure to radiofrequency (RF) radiation. Because base station installations and telecommunication networks are growing, there is a growing need to address the health risks connected with exposure to telecommunication masts. Using the Electrosmog Meter Cornet Model, power density from many telecom masts owned by various network operators was measured in this investigation. At 10-meter intervals, the RF radiation in seven (7) settlements in Yenagoa town, located in the Yenagoa Local Government Area of Bayelsa State, was measured within radial distances of 100 meters. With a mean value of 4.0569mWm-2, the measured values vary from 0.650mWm-2 to 9.810mWm-2. Still, values evolved. Nevertheless, additional factors, such as adjacent electromagnetic sources' wave interference or reference base station interference, caused readings to fluctuate. It was discovered that the greatest power density level was 9.810 mWm-2, and it was measured 20 meters away from the base station at site MBS1. As per the International Commission on Non-ionizing Radiation Protection (ICNIRP) and other regulatory authorities, the standard limit of 4.5Wm-2 for the 900 MHz system is not exceeded by the radiation exposure level, as the findings show. This shows that the exposure levels in these areas are low enough to not seriously jeopardize the health of those living in the research area.

Wireless power and information dual transfer system via magnetically coupled resonators

High-efficiency medium-range wireless power transfer using magnetically coupled resonators requires a wireless data link between the contactless coils to regulate power. Multiplexing the power transfer channel as the information channel is a cost-effective solution for the communication. However, existing technologies cannot transmit data across the medium-range magnetically coupled resonators channel without substantially affecting power transfer. Here we show a power-electronics-converters based wireless power and information dual transfer system in which the information signals are modulated on one dc side of the inverter/rectifier, and transmitted through a conventional medium-range wireless power transfer system, and then demodulated on the other dc side. Using the frequency mixer characteristic of the inverter/rectifier, information is modulated onto the sideband of the power carrier and transmitted through the medium-range channel. Finally, we prototyped a 6.78 MHz system capable of transferring 45 W power across a one-meter distance with 62% efficiency and 60 kb/s bitrate for half-duplex communication.

Simultaneous equatorial plasma bubble observation using amplitude scintillations from GNSS and LEO satellites in low-latitude region

This study estimates the scale sizes of the plasma density irregularities and the longitudinal width associated with equatorial plasma bubbles (EPBs) in equatorial and low-latitude regions. By analyzing amplitude scintillation S4 indices and total electron content (TEC) measured from low earth orbit (LEO) satellite’s beacon signals with 400 MHz and Global Navigation Satellite System (GNSS) L1/E1 signals with 1575.42 MHz, recorded by receivers at the KMITL station in Bangkok, Thailand (geographic; 13.73° N, 100.77°E, magnetic: 7.26°N), we investigate the characteristics of these irregularities. We collected data of 154 LEO satellite pass events during nighttime on 21 disturbed days in four equinoctial months in 2021. Based on the presence or absence of the scintillation effects on GNSS and LEO beacon signals, the events are categorized into four classes to estimate the scale size of the plasma density irregularities. The analysis suggests that events with both GNSS and LEO scintillations, as well as events with GNSS scintillation alone, occur predominantly before midnight assuming the presence of the small-scale size of the irregularities within EPB. However, events with only LEO scintillation occur throughout the whole night and some events are observed before the events with both GNSS and LEO scintillations. Post-sunset LEO scintillation alone may be attributed to the onset of EPBs developing at low altitude, while post-midnight LEO scintillation events near the magnetic equator, observed during periods of low GNSS Rate of TEC Index (ROTI) values, are associated with bottom-side ionospheric irregularities but are not linked with EPB. The findings are consistent with previous researches on the generation and decay of electron density irregularities within plasma bubbles. However, this study provides new insights by using specific data sets and analysis techniques, offering a more comprehensive understanding of the association of LEO scintillations with bottom-side ionospheric irregularities near the magnetic equator, not observed in the ROTI map.Graphical

Assessment of High Frequency Imaging and Doppler System for the Measurements of the Radial Artery Flow-Mediated Dilation

Objectives: In the article we describe the new, high frequency, 20 MHz scanning/Doppler probe designed to measure the flow mediated dilation (FMD) and shear rate (SR) close to the radial artery wall. Methods: We compare two US scanning systems, standard vascular modality working below 12 MHz and high frequency 20 MHz system designed for FMD and SR measurements. Axial resolutions of both systems were compared by imaging of two closely spaced food plastic foils immersed in water and by measuring systolic/diastolic diameter changes in the radial artery. The sensitivities of Doppler modalities were also determined. The diagnostic potential of a high frequency system in measurements of FMD and SR was studied in vivo, in two groups of subjects, 12 healthy volunteers and 14 patients with stable coronary artery disease (CAD). Results: Over three times better axial resolution was demonstrated for a high frequency system. Also, the sensitivity of the external single transducer 20 MHz pulse Doppler proved to be over 20 dB better (in terms of a signal-to-noise ratio) than the pulse Doppler incorporated into the linear array. Statistically significant differences in FMD and FMD/SR values for healthy volunteers and CAD patients were confirmed, p-values < 0:05. The areas under Receiver Operating Characteristic (ROC) curves for FMD and FMD/SR for the prediction CAD had the values of 0.99 and 0.97, respectively. Conclusions: These results justify the usefulness of the designed high-frequency scanning system to determine the FMD and SR in the radial artery as predictors of coronary arterial disease.

Design and performance of a 16-channel coarse-fine TDC prototype ASIC

This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20.48μs and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW.

An Independent Dual-Coil Driving Topology for Wireless Power Transfer

The existing dual-coil driving topology mostly adopts two inverters or additional switching circuit, which increases the cost and size, and the complexity of the wireless power transfer (WPT) system. In this letter, a novel inverter topology with independent dual-coil driving capability is proposed for WPT applications, where the main switch and auxiliary switch can drive two independent coils. Moreover, this topology not only offers wide zero voltage switching range and compact size, but also improves the output power and coil utilization. Meanwhile, a quadruple D square (QDS) coil with uniform magnetic field is discussed with the dual-coil driving topology. The detailed parameters design of the proposed topology is discussed and the QDS coil is compared with other coils in terms of magnetic flux intensity. Finally, a 1MHz and 220W wireless power transfer system is built to verify the proposed topology and coil structure.

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

AbstractAn ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.

A Fully Integrated 0–200-MHz System BW Wireless Direct Sampling Receiver in 14-nm FinFET

This paper presents a fully-integrated wireless direct sampling receiver that covers from DC to 200MHz system bandwidth implemented with a single-channel SAR ADC in 14nm FinFET. To demonstrate the proposed architecture, frequency modulation (FM) among the applicable standard frequency bands is adopted as a prototype. The measured demodulated SNR is 73.9dB with -47dBm input power at 108MHz and the sensitivity level is -106dBm. The proposed direct sampling receiver shows a robust performance over a 30dB demodulated SNR even in the presence of the interference such as a strong adjacent channel and an in-band spur. Furthermore, the FM channel scan time is drastically reduced since the proposed receiver simultaneously samples all channels without adjusting analog building blocks.

An Inductor-First Single-Inductor Multiple-Output Hybrid DC–DC Converter With Integrated Flying Capacitor for SoC Applications

With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple-output (SIMO) inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual-switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with the maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with 500MHz system clock to achieve a less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology.

The development of simple microcontroller-based QCM with some treatment on the crystal oscillator surface

The low-cost quartz crystal microbalance (QCM) instrument with the microcontroller as the basis of the embedded system of the frequency counter was implemented. The system uses a quartz crystal transducer from the crystal oscillator component. The frequency shifting was observed and analysed in association with some experimental tests. The experiments such as ethanol evaporation, water vapor in the humidity chamber, and coating the surface with TiO2 particles had been conducted. The developed QCM instrument has shown the ability to measure the frequencies in response to the addition or reduction of mass on the surface of the crystal oscillator. These responses are caused by evaporation, humid condition, and deposited particle on the quartz crystal surface. The QCM was varied into two initial frequencies, 5 and 10 MHz. The 5 MHz system represents the proper “in range” frequency counters, inside a counting limit of the microcontroller up to 5.6 MHz. On the other side, the 10 MHz is an experimental development system. Both types utilise a D flip-flop frequency divider that made a microcontroller-based frequency counter and can count the frequency twice the limit. The more stable 10 MHz have shown promising potential application related to the surface interaction with other material and can hold thicker deposition on its surface with a better stability response than the lower frequency counterpart.

Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq-7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios.

Integrating TDR and GPR methods to study the structure of peatland

Abstract. In this study we compared time-domain reflectometry (TDR) data from boreholes and the results of ground-penetrating radar (GPR) along the cross-sections on a peat deposit. The studied mire located on the Zaonezhye Peninsula (Republic of Karelia, Russia); its structure included layers of peat and bedding lake sediments. To perform the measurements we used GPR with antenna unit 150 MHz and TDR system TDR200 with probe. The mire structure was characterized by a medium basin structure (7 m max depth) and sloping mire topographic. Comparison TDR and GPR data yielded similar dielectric constant values for peat layers. The average mistake in dielectric constant values between TDR and GPR observation was 5 units. The conditions for the formation of interfaces on GPR cross-sections were studied by analyzing dielectric constant change across the peat deposit. We found that the depth positions of the GPR interfaces were quite accurately ( 20 cm) coincides with the intervals of the change of peat type. Our results indicate the difficulty of interpreting GPR cross-sections contained multi-reflectors for subsurface with sub-horizontal structure such as peat deposits or lakes bottom sediments.

Low-Latency QC-LDPC Encoder Design for 5G NR.

In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection mechanism using a radioactive source. These results prove that the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify that it can work up to about 3 Gbps, while they also indicate that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

Lossless Decompression Accelerator for Embedded Processor with GUI.

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

An FPGA-based IP for recognizing violence against children

We present in this paper an FPGA-based IP for recognizing most common violent actions against children (VACR IP). VACR IP uses only skeleton joints data as inputs to keep the privacy of people inside their homes or in the schools. The proposed hardware achieved a detection rate of 97.72%, processing speed 761FPS, and a latency value equals to 2.79msec using a 50MHz system clock.In sum, this research method presents:•First FPGA-based IP for recognizing most common child abuses without any privacy breach of people real images by using only skeleton joints data.•The IP can detect the violence and the type of the violent action.•The IP can be embedded in complete systems to be installed in schools by school psychologists and counselors.

Signal transmission of 4 GHz beyond the system bandwidth in UV-C LED communication based on temporal ghost imaging

Due to the bandwidth limitation of the ultraviolet-C (UV-C) optical communication system and strong channel attenuation, it is difficult to transmit high-frequency signals. In this paper, the temporal ghost imaging (TGI) algorithm was first applied to the UV-C communication experimentally, and we realized the transmission of a 4 GHz signal through 95.34 MHz system bandwidth. The study indicates that the TGI algorithm can significantly improve the signal-to-noise ratio (SNR) compared with the on–off keying method. Our research provides a new approach for alleviating transmission frequency limitation due to poor SNR and insufficient hardware bandwidth.

Subnanosecond Time Synchronization Using a 100Base-TX Ethernet Transceiver and an Optimized PI-Clock Servo

This work presents a real-time 100Base-TX Ethernet physical layer (PHY) transceiver chip implemented in a 180-nm technology. The PHY chip implements highly accurate hardware timestamping by using an 8-bit digital-to-phase converter (DPC) generating 256 phases of the 125 MHz system clock. Using these clock phases, spaced 31.25 ps apart from each other, phase relationships can be evaluated to timestamp ingress and egress frames with improved resolution. Connected by up to 120-m-long category five unshielded twisted-pair cables, two of these PHY chips are used to demonstrate the synchronization in a two-node scenario. A proportional-integral (PI)-clock servo is used at the slave for the synchronization. To optimize the performance, the parameters of the controller need to be chosen carefully. To do so, a simple model is used to find a suitable bandwidth of the controller as a tradeoff between the noise of the timestamping and the noise of the oscillator. All in all, a synchronization accuracy with a standard deviation of only 64 ps and a mean offset of well below 100 ps is achieved in the given scenario. To the best of our knowledge, this is the highest synchronization accuracy over copper-based Ethernet reported to date.

High-speed gaze detection using a single FPGA for driver assistance systems

The performance of driver gaze detection by video-based eye-tracking often encounters problems in lowcomputing speed, high-power consumption, and installation space constraints inside the vehicle. In this paper, we present an eye-tracking system that uses a single field-programmable-gate-array chip to overcome the aforementioned problems. In the detection system, the image quality is 640 $$\times$$ 480 pixels with an 80 fps frame rate. Eye feature extraction is conducted using the enhanced semantics-based vague image representation approach. A succinct fully-connected neural network is then employed to classify various directions of sightline. Our experimental results exhibited a noticeable recognition speed at 0.52 $$\upmu$$ s using a 100 MHz system clock and had an average detection rate of 92%.

First observations of Polar Mesospheric Echoes at both 31 MHz and 53.5 MHz over Svalbard (78.2°N 15.1°E)

AbstractDuring summer 2020, observations of the mesosphere using a 53.5 MHz radar on Svalbard, at 78.2°N 15.1°E, revealed the well-known Polar Mesospheric Summer Echoes (PMSE). At the same time, a co-located meteor detection radar, operating at 31 MHz detected corresponding echoes very distinct from those associated with meteor trails. Comparing as many days as possible during 2020, incontestable evidence arose to demonstrate that the meteor detection radar was capable of observing PMSE, although not in the optimised fashion of the 53.5 MHz system. We present examples of results from both systems, supplementing the earlier findings of Swarnalingam et al. (2009), and simultaneously show very first results from this particular geographical location.