MHz Signal Frequency Research Articles

A Picometre-Level Resolution Test Method without Nonlinearity for Heterodyne Interferometer Measurement Electronics

The wide application of displacement measurement in high-precision equipment production and high-precision metrology is placing increasing pressure on the resolution of heterodyne interferometers. However, as the core component of an interferometer, since measurement electronics includes the cross-physical process of photoelectric conversion, its resolution is rarely evaluated, either on an individual level or as a whole. Therefore, in this paper, we propose a picometer resolution test method for measurement electronics, that uses intensity modulation signals based on an AOM to replace the beat frequency interference signals, and an ordinary commercial guide rail to equivalently generate the pm-level displacement of the heterodyne interferometer under laboratory conditions. Based on the detailed analysis of the type of noise in the test device, the correlation between the light intensity and the nonlinear error was established, and nonlinearity was suppressed to 10% of the original level. Furthermore, this test method allows one to perform a 0.1 mrad phase step test at 1 MHz signal frequency, equivalent to a 2.5 pm resolution test in a double-pass heterodyne interferometer. Simultaneously, it can be directly applied to the resolution test for measurement electronics with a center frequency in the range of 1 MHz to 20 MHz.

Nanosecond-response Cu(In,Ga)Se2 self-powered photodetectors enhanced by the back contact modification

Cu(In,Ga)Se2 (CIGS) thin film device is very promising in the family of free-space self-powered photodetectors. Response speed is the core indicator of a photodetector. However, until now, response time of CIGS-based photodetectors still limited to the μs level, which is much lower than high quality Si/Ge, InGaAs photodetectors, as well as new type graphene, perovskite photodetectors. In this work, we first report an ultrafast Mo/CIGS/CdS/ZnO/ITO photodetector with 50 ns response time and 1.5 MHz −3 dB bandwidth. Even under 3 MHz signal frequency, it can still work stable and reliable. Detail research show that Mo electrode is the limitation of the performance. When the diffraction peaks changed from (110)/(220) and (221) to quasi-single (110)/(220), which representing the decrease of crystal orientation, the Mo film will become more uniform, dense and straight, and concomitant high resistant MoSe2at the Mo/CIGS interface significantly reduces from ∼ 1900 to ∼ 100 nm and become discontinuous, which is the key point for the device performance. This work shows the tremendous potential of CIGS device in the field of ultrafast photodetection.

A wide linear range CMOS OTA and its application in continuous-time filters

In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency continuous time filters. A second-order fully differential filter architecture is also implemented by using this proposed OTA. The linear OTA and the filter are implemented in SCL 180 nm CMOS process technology with 1.8 V supply voltage. The proposed OTA achieves third order harmonic distortion ($${\textit{HD}}_3$$) of $$-\,74.3$$ dB, inter modulation distortion ($${\textit{IM}}_3$$) of $$-\,75.5$$ dB for $$600\,\hbox{mV}_{p-p}$$ differential input with 1 MHz signal frequency and a linear range of 0.9 V for 1% transconductance variation. The filter is designed for 100 kHz cutoff frequency and achieves $${\textit{HD}}_3$$ of $$-\,68.75$$ dB and $${\textit{IM}}_3$$ of $$-\,64.3$$ dB for $$300\,\hbox{mV}_{p-p}$$, 10 kHz input signal.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of . Index Terms—Digital-to-analog converter (DAC), interleaving, return-to-zero (RZ), spurious-free dynamic range (SFDR).

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

Radio-Frequency Magnetometry Using a Single Electron Spin

We experimentally demonstrate a simple and robust protocol for the detection of weak radio-frequency magnetic fields using a single electron spin in diamond. Our method relies on spin locking, where the Rabi frequency of the spin is adjusted to match the MHz signal frequency. In a proof-of-principle experiment we detect a 7.5 MHz magnetic probe field of ~40 nT amplitude with <10 kHz spectral resolution. Rotating-frame magnetometry may provide a direct and sensitive route to high-resolution spectroscopy of nanoscale nuclear spin signals.

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm2, among which the area of the current-source block is only 0.28 mm2. The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.

A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.

A New Type of Transistor with Application for High Sensitive Imaging

A new bipolar type semiconductor device is proposed, fabricated by two diffusion processes and integrated with no isolation region. The device has a small n+-diffused gate electrode instead of an insulating gate in the MOS transistor. It was expected and confirmed that the device could be used as a switching transistor controlled by the gate electrode. Applying this switching characteristic, the current amplification effect in the hook structure and charge storage concept of pooto diode, a high sensitivity photo sensor has been constructed. Several Lux·sec sensitivity and mA order signal current is observed. A self scanned image sensor has been constructed by the device with PCD scanner. This has been successfully operated at a 2 MHz signal frequency. Moreover, this device operates as JFET, punch through transistor and some current amplification devices.