MHz Long-term Evolution Signal Research Articles

Bandpass Filtering Power Amplifier With Wide Stopband and High Out-of-Band Rejection

In this brief, a power amplifier (PA) with excellent integrated filtering characteristics is presented. The designed process is based on a novel impedance transformer (IT) consisting of cascaded coupled-line sections with stubs. The proposed IT generates four transmission zeros (TZs), which not only greatly improves the frequency selectivity, but also improves the second harmonic suppression performance, further enhancing the linearity of the PA. For demonstration, a bandpass filtering PA is designed, fabricated, and measured. The designed PA exhibits both good filtering bandpass response and power amplification. The rejection levels are larger than 59.7 and 69 dB for the lower and higher suppression bands. Meanwhile, the measured drain efficiency (DE) of the constructed PA is 58.5%-73% with a large-signal gain of 8.9-10.2 dB at 1.85-2.1 GHz. Besides, using a 20 MHz long-term evolution signal as the driving signal for the PA, the adjacent channel power ratio is lower than −57.8 dBc.

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

PurposeThe purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).Design/methodology/approachThe CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.FindingsFor driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.Originality/valueIn this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Physical Layer and MAC Design for Self-Reliant Cognitive Multicast Networks Using LTE Resources

Existing Long Term Evolution (LTE) networks have untapped radio frequency resources, also known as white space, that can be repurposed for cognitive radio applications. A secondary network can opportunistically interweave communication within the white space of an existing LTE signal by leveraging cognitive radio. In this article, we present CIAO-LTE, a novel framework for forming a cognitive interwoven self-reliant secondary network with no additional physical infrastructure, collaboration from the existing primary network, and software or hardware changes in the primary LTE network. For medium access control, CIAO-LTE uses an adapted version of Slotted ALOHA with a no-back-off contention. We analyze parameter settings and conduct extensive simulations to validate performance. The simulation results show that CIAO-LTE achieves throughputs as high as 4.75 Mb/s on a 5MHz LTE signal and approximately 19Mb/s with a 20MHz LTE signal, and average packet delays within a few milliseconds.

Efficiency and linearity enhancement of a two‐stage X‐band PA through simultaneous gate and drain supply modulation

This study addresses an analogue method for mitigating the non-linearities introduced by discrete supply modulation of a high-efficiency power amplifier (PA). A 10 W two-stage X-band gallium–nitride monolithic microwave integrated circuit ( PA with a peak power-added efficiency of 55%, is tested with drain supply modulation from 10 to 20 V with an increase in efficiency and substantial degradation in linearity. In this work, the authors characterise the two-stage PA dynamically to develop shaping functions for both gate bias voltages. They demonstrate that gate modulation can improve back-off gain and linearity, specifically when gate biases of the two stages of a PA are independently modulated. Simultaneous gate and drain modulation results in 15 percentage point improvement in efficiency over a static supply, and a consistent improvement in noise power ratio over a static supply, for a 20 MHz noise-like signal. Results with a 20 MHz long-term evolution signal show comparable improvement in efficiency while maintaining adjacent channel power ratio near the level of the PA with a static supply.

Flexible bandwidth reduction technique for envelope tracking using low‐pass finite impulse response filters

In this Letter, low-pass finite impulse response filters are proposed to flexibly reduce the envelope bandwidth (BW) requirements for envelope tracking (ET) supply modulators. A second-order power ET (PET) approach is used as a comparative study, and a `design zone' for shaping function coefficients is identified for the first time. Proposed 20 and 10 MHz low-pass filters (LPFs) are used to reduce the effective envelope BW in response to a 20 MHz long-term evolution signal applied to a 10 W power amplifier (PA). Experimental results verify that in comparison with PET, the proposed LPF method has the benefit of allowing arbitrary BW reduction and is compatible with the use of customised shaping functions. It is also shown that significant memory effects can be introduced when the effective envelope BW is reduced to less than the RF BW. To investigate the linearisability of the ET PA, the linearity before and after digital pre-distortion is also measured.

Modulated rapid load pull system for the emulation of envelope tracking power amplifiers

This Letter presents a novel characterisation system that is able to fully emulate a complete envelope tracking power amplifier (ET-PA) environment, with modulated impedance synthesis and dynamic supply voltage generation while using industry-standard modulated signals and digital pre-distortion. The system is used to characterise a 10 W GaN device and provide impedance control over the signal and distortion bandwidths, in response to a 10 MHz long-term evolution signal. A National Instruments PXI-based measurement system is utilised to apply tracking signals to a bespoke supply modulator and successfully improve the average power added efficiency by ~18 percentage points. Three different shaping functions are implemented, and their efficiency and linearity performance evaluated. In addition, digital pre-distortion (DPD) is used to linearise the PA while operating with the three different tracking trajectories. Experimental results demonstrate that when applying shaping functions, a trade-off needs to be made between efficiency and linearity. Even though a constant gain shaping function provides lower efficiency, it achieves good raw linearity performance without DPD, which is a good option if local linearisation is not available. This novel system is a useful tool in the design of ET-PAs, to more completely investigate the performance of the device.

Broadband continuous mode power amplifier with on‐board harmonic injection

This study presents the design of a broadband continuous mode power amplifier (PA) with an active harmonic injection (HI). Since the injected harmonic signal is generated on-board using a frequency doubler, this design has a single radio frequency input. The generated second harmonic is injected at the drain terminal of a gallium nitride high-electron-mobility transistor used in designing continuous class B/J PA. A design space in terms of amplitude and phase of the injected harmonic signal is analysed to obtain the loads that operate the PA in the continuous class B/J mode at the current generator reference plane. The proposed design strategy is verified by designing a prototype with a frequency doubler and a PA using 10 and 15 W gallium nitride high-electron-mobility transistors, respectively. The measured drain efficiency of 60.04-70.96% and output power of 40.17-42.6 dBm is obtained from 1 to 1.9 GHz. This corresponds to a broadband operation of 900 MHz with 62% fractional bandwidth. The designed HI-PA is also tested with a 20 MHz long-term evolution signal whose corresponding adjacent channel power ratio is better than -47.76 dBc in the overall band after applying digital predistortion.

Hybrid SI cancellation for single‐antenna full‐duplex radios

A hybrid self-interference (SI) cancellation scheme, composed of a two-tap analogue canceller and a digital multi-path SI canceller, is proposed for single-antenna full-duplex radios. The analogue canceller mitigates the two strongest components of the SI to prevent saturating the receiver. The digital canceller deploys an auxiliary receiver chain to capture the RF-transmitted signal to mitigate the residual multi-path SI signal. As the proposed scheme uses the RF-transmitted signal as reference, the transceiver impairments such as power amplifier non-linearities and phase noise are suppressed along with the SI. Experiments have validated the effectiveness of the proposed scheme on a 20 MHz long-term evolution signal of +20 dBm power.

A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS

A CMOS class-E outphasing RF power amplifier is presented with a new passive combining circuit that provides high efficiency and high output power. An efficiency enhancement circuit and a power enhancement circuit are proposed as part of the combiner that improve efficiency at power back-off and increase output power without violating reliability limits, respectively. The proposed power amplifier is designed in a 45nm CMOS technology. The power amplifier (PA) delivers 29.5 dBm peak output power at 2.4 GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off, and 21.16% drain efficiency at 6 dB power back-off. The proposed power amplifier shows excellent linearity with digital pre-distortion. Better than -50 dBc adjacent channel power ratio (ACPR) is obtained with 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth. For two-carrier 20 MHz LTE signal, -44 dBc ACPR is achieved. 21% average drain efficiency is obtained with LTE signal with a 6 dB peak-to-average power ratio. The PA is also tested with 802.11g WLAN signal and it satisfies the spectral mask requirement with high margin. 1.4% (-37.1 dB) error vector magnitude (EVM) is obtained with LTE signal (64-QAM) with a 10 MHz bandwidth.

Multiobjective Bayesian Optimization for Active Load Modulation in a Broadband 20-W GaN Doherty Power Amplifier Design

This paper proposes a multiobjective Bayesian optimization strategy to deal with the complex matching problem of designing a broadband 20-W gallium nitride Doherty power amplifier (DPA). Applying the proposed method, the DPA’s matching networks are optimized to align the desired and the realized impedance trajectories both at saturation and power backoff from 1.5 to 2.4 GHz. By combining a programming environment with the commercial electronic design automation (EDA) software, the optimization process is implemented automatically. Comparison designs reveal that the proposed method outperforms the built-in optimizer of the commercial EDA software for broadband DPA designs. When tested with a single-carrier 20 MHz long-term evolution signal, the measured results show that the DPA achieves an average efficiency of 45.3%–53.6% at 7 dB backoff across the band, with the adjacent channel power ratio levels better than −45.6 dBc after using digital predistortion.

Analysis and design of class-O RF power amplifiers for wireless communication systems

In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are common-source (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P$$_{1\,{\mathrm{dB}}}$$1dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 $$\%$$% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than ź30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 $$\%$$%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Dual-Mode CMOS Doherty LTE Power Amplifier With Symmetric Hybrid Transformer

This paper presents a dual-mode Doherty long-term evolution (LTE) power amplifier (PA) for efficiency enhancement at power back-off. The amplifier utilizes transformer-based Doherty operation to achieve high back-off efficiency with good linearity. In addition, the PA has two power modes to further reduce the power consumption when low output power is required. The PA combines four push-pull amplifiers by using an symmetrical hybrid transformer that ensures low combining loss and high amplifier efficiency. The two-stage LTE amplifier is fabricated in standard 40 nm CMOS technology and it achieves 28 dBm output power with 1.5 V supply. The peak power-added efficiency (PAE) of the amplifier is 34% and the PAE at 6 dB and 12 dB back-off levels are still as high as 25.5% and 19.7% respectively. The amplifier is tested with 20 MHz LTE signal and it satisfies the stringent ACLR and EVM requirements at 23.4 dBm output power with a PAE of 23.3%. In addition, the amplifier achieves 18.4% PAE when 6 dB lower power is transmitted and 11.1% PAE at 12 dB back-off under LTE modulation.

Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator

In this paper, the bandwidth of the delta sigma modulator (DSM)-transmitter is improved using low complexity time-interleaved DSM. The high clock speed requirement of DSM is the main limitation to increase the signal bandwidth in DSM-transmitter. In this research, the bandwidth of DSM-transmitter is increased four times by using low complexity four-branch time-interleaved parallel DSM without the need for increasing clock speed. This low complexity parallel DSM is designed based on polyphase implementation technique. Then, the transmitter architecture is simulated using MATLAB simulink and Advanced Design System (ADS). For this simulation, the uplink long-term evolution (LTE) signal with different bandwidths of up to 7.68MHz is used. The simulation shows that by using four-branch time-interleaved parallel DSM in transmitter architecture for 7.68MHz LTE signal with oversampling ratio (OSR) of 16, the signal to noise and distortion ratio (SNDR) is about 41dB with the clock speed of only 30.72MHz. This is four times lower than the required clock speed of the conventional transmitter to achieve the same SNDR.

Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

Inductor‐less envelope modulated radio frequency power amplifier using stacked amplifiers and envelope shaping

An envelope modulated radio frequency (RF) power amplifier (PA) is presented using a `stacked amplifiers' modulator. The modulator combines the efficiency of class G with the convenience of a charge pump. Since it is a single band modulator, no large inductors or transformers are required. A two level prototype has been developed and tested with a 7.5 dB peak-to-average power ratio 1.4 MHz bandwidth long term evolution (LTE) signal. Envelope shaping was used to improve linearity. Individually the modulator achieved between 54 and 60% efficiency, dependant on the envelope shaping function. When combined with a suitable class E PA, 40% DC to RF efficiency was achieved at 1.38 W output power with the 1.4 MHz LTE signal.

Design of Broadband Linear and Efficient Power Amplifier for Long-Term Evolution Applications

In this letter, a broadband linear and efficient power amplifier for base-stations in long-term evolution (LTE) applications is designed, fabricated, and experimentally verified, employing Cree's CGH40010F GaN HEMT. A novel method of baseband, fundamental and harmonic impedances control is used to provide high linearity and efficiency across a broad bandwidth. When producing a two-tone carrier-to-intermodulation ratio (C/I) of 30 dBc, the circuit has demonstrated a two-tone power added efficiency (PAE) between 45%-60% across the frequency range from 1.6 to 2.6 GHz while delivering 36.0-38.5 dBm average output power. For a single-carrier 20 MHz LTE signal with a peak-to-average ratio (PAR) of 6.5 dB, a measured high PAE of 40%-55% can be achieved at an average output power of 35.3-37.5 dBm with an adjacent channel leakage ratio (ACLR) of about -30 dBc from 1.6 to 2.6 GHz.

Highly efficient unsymmetrical doherty power amplifier with DPD for LTE application

This article presents a highly efficient Doherty power amplifier (DPA) with 4.4% relative signal bandwidth for long-term evolution (LTE) application at frequency band of 450–470 MHz.To maintain high efficiency at large back-off power (BOP), the DPA is unsymmetrical and the carrier and peaking amplifiers are implemented to show unequal saturation power. Experimental results using continuous wave signal indicate a power-added efficiency (PAE) of 64.3% at saturation power of 49.9 dBm and a PAE of 62% at about 6-dB BOP. For 20 MHz LTE signal, the adjacent channel leakage ratio is −30 dBc and can be improved to −49 dBc by using the digital predistortion technique at an average output power of 41.5 dBm with a PAE of 51%. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2352–2356, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27043